Memory DLL Clock Gating for Low-Power Idle Operation
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Solution Overview
Problem
Dynamic random access memory (DRAM) chips in computer systems face high power consumption due to the need to maintain delay-locked loops (DLLs) in idle mode, as turning them off results in significant turn-on latency, leading to inefficiencies in power management.
Innovation Solution
A memory device with a clock gating circuit, referred to as the command and address clock (CAclk) pulse swallower, which modifies the clock signal to apply a reduced activity clock to the DLL during idle mode, reducing power consumption by selectively masking clock pulses and maintaining the DLL's ability to track voltage and temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL is turned off during idle mode, then power consumption is reduced, but turn-on latency increases significantly due to re-locking requirements
Solution Approach 1:
The DLL remains in a pre-initialized state during idle mode, maintaining basic operational readiness without full activation. This preliminary state allows the DLL to quickly transition to full operation when needed, avoiding the significant re-locking time that would occur if completely powered down.
Solution Approach 2:
The system dynamically adjusts the DLL's operational state based on activity requirements. During idle mode, the DLL operates in a low-power reduced activity clock mode rather than being completely off or fully active, allowing adaptive power management without sacrificing rapid response capability.
2Loss of time
If the DLL remains on during idle mode, then turn-on latency is avoided, but power consumption increases
Solution Approach 1:
Instead of continuous full-operation clocking, the system applies a reduced activity clock during idle mode that provides periodic updates sufficient to maintain DLL functionality and tracking capability while significantly reducing power consumption compared to continuous full-speed operation.
Solution Approach 2:
The clock activity factor is changed from full operation to reduced activity during idle mode. This parameter change allows the DLL to maintain its locked state and tracking capability while consuming less power, as the reduced clock frequency requires less energy for operation.
3Use of energy by moving object
If a reduced activity clock is applied to the DLL during idle mode, then power consumption is reduced, but the ability to track voltage and temperature changes may be compromised
Solution Approach 1:
The reduced activity clock provides partial clocking action during idle mode, which is sufficient to maintain basic DLL tracking of voltage and temperature changes. While not as robust as full-speed operation, this partial action maintains adequate tracking capability for idle conditions while achieving significant power savings.
Data Source
AI summary
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.