Semiconductor Memory DLL Clock Locking Across Variable Frequencies
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Solution Overview
Problem
Existing DLL circuits in semiconductor memory apparatuses face inefficiencies in clock phase synchronization and data output timing, particularly when dealing with varying clock frequencies, leading to delayed data access and increased development costs due to the need for frequency-dependent clock dividers and terminal connections.
Innovation Solution
A DLL circuit with a frequency sensing unit, clock dividing unit, and phase sensing unit that selectively divides and switches phase control signals based on the external clock frequency, allowing for efficient phase locking of internal clocks without requiring frequency-dependent clock dividers or terminal switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DLL circuit uses a fixed clock divider configuration, then the circuit structure is simple, but it cannot adapt to different clock frequencies leading to synchronization errors
Solution Approach 1:
The patent implements a dynamic clock divider that automatically adjusts its division ratio based on the detected external clock frequency. The circuit includes a frequency detection mechanism that senses the external clock frequency and dynamically selects between different division ratios (e.g., 1:2 or 1:4) to ensure the internal clock remains at a stable frequency regardless of external clock variations, thus resolving the contradiction between adaptability and complexity.
2Speed
If the internal clock frequency is kept high for fast data access, then data access speed is improved, but phase locking becomes difficult at low external clock frequencies
Solution Approach 1:
The patent employs a dynamic frequency adjustment mechanism where the clock divider ratio is automatically changed based on the external clock frequency. When the external clock frequency is low, the circuit selects a larger division ratio to prevent the internal clock from becoming too high, ensuring stable phase locking. When the external clock frequency is high, the circuit uses a smaller division ratio to maintain fast data access speed, thus resolving the contradiction between speed and reliability.
3Measurement precision
If frequency-dependent clock dividers and terminal switches are used to handle different clock frequencies, then clock synchronization accuracy is improved, but development costs and device complexity increase
Solution Approach 1:
The patent merges the frequency detection function and clock division function into a single integrated circuit block. The frequency detector and clock divider are combined such that the same circuit structure performs both frequency sensing and adaptive division, eliminating the need for separate frequency-dependent clock dividers and terminal switches. This integration maintains clock phase synchronization accuracy while significantly reducing development costs and circuit complexity.
Data Source
AI summary
A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.