Semiconductor Memory DLL Clock Signal Generation and Output Enable Control
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high-speed, low-power, and miniaturized designs due to increased CAS latency values, which result in slower counter operation speeds and larger circuit areas, as well as continuous power consumption until a read command is applied.
Innovation Solution
A semiconductor memory device utilizing a delay locked loop and an output enable control circuit with a minimized counter structure, featuring a first and second variable delay line, phase detection, and a control signal generation unit to generate an output enable signal based on CAS latency information and delay times, allowing for efficient operation without continuous counting and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CAS latency value increases to accommodate higher memory speeds, then the operating speed is improved, but the counter operation speed decreases and circuit area increases
Solution Approach 1:
The patent segments the counter operation into two distinct phases: a locking operation phase where the counter operates continuously at high speed, and an output enable signal generation phase where the counter operates only when needed. This segmentation allows the counter to maintain high operating speed during locking while reducing unnecessary operations during CAS latency periods, thereby resolving the contradiction between memory speed and counter operation speed.
Solution Approach 2:
The patent implements periodic action by enabling the counter only during specific periods (locking operation and output enable signal generation) rather than continuously. The counter is controlled to operate periodically based on the phase detection results and CAS latency requirements, which maintains high counter operation speed while accommodating increased CAS latency values for higher memory speeds.
2Speed
If the CAS latency value increases to accommodate higher memory speeds, then the operating speed is improved, but the circuit area increases
Solution Approach 1:
The patent segments the counter control into distinct operational phases (locking vs. output enable generation), allowing the use of a smaller counter structure that operates efficiently only when needed. This segmentation eliminates the need for large counters that would be required if continuous high-speed operation were maintained, thereby reducing circuit area while supporting higher memory speeds.
Solution Approach 2:
The patent applies dynamics by making the counter operation adjustable and phase-dependent rather than static and continuous. The counter's operation is dynamically controlled based on the detected phase relationship between external and DLL clock signals, allowing the circuit to use minimal resources (small counter area) while achieving high performance when needed.
3Measurement precision
If the counter operates continuously to maintain synchronization, then the timing accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic action by controlling the counter to operate only during specific phases (locking operation and output enable signal generation) rather than continuously. This periodic operation maintains timing synchronization accuracy when needed while significantly reducing power consumption during idle periods, directly resolving the contradiction between timing precision and power usage.
Solution Approach 2:
The patent extracts the essential counter operation from continuous operation by identifying and isolating only the critical phases where counter operation is necessary (locking and output enable generation). This extraction eliminates unnecessary power consumption while preserving timing synchronization accuracy during the essential operational phases.
Data Source
AI summary
A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.