Semiconductor Memory DLL Clock Switching for Phase Locking
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Solution Overview
Problem
Existing DLL circuits in semiconductor memory apparatuses face inefficiencies in clock phase locking due to high frequency external clocks causing inactivity of feedback clocks and requiring costly and time-consuming selection of clock dividers based on external clock frequency.
Innovation Solution
A DLL circuit with a frequency sensing unit generating high or low frequency signals based on CAS latency, a clock dividing unit dividing the internal clock frequency, and a phase sensing unit switching reference and comparison clocks to selectively switch phase control signals, allowing efficient phase locking of internal clocks regardless of external clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock divider is selected based on external clock frequency, then the feedback clock can be generated correctly, but the device complexity and development cost increase due to multiple clock divider selections and terminal connection changes
Solution Approach 1:
The phase sensing unit is designed to universally handle both high-frequency and low-frequency external clocks by selectively switching between the internal clock and divided clock as the comparison clock, eliminating the need for separate feedback paths for different frequency ranges. This multi-functional design allows a single phase sensing unit to perform phase comparison regardless of the external clock frequency.
Solution Approach 2:
The system dynamically switches the comparison clock source based on the external clock frequency detected by the frequency sensing unit. When the external clock is high-frequency, the internal clock is used as the comparison clock; when low-frequency, the divided clock is used. This dynamic adaptation allows the feedback clock generation to maintain reliability without requiring multiple fixed configurations.
2Reliability
If the internal clock is used as the comparison clock for high-frequency external clocks, then phase locking can be achieved, but the phase locking efficiency decreases due to the large frequency difference between clocks
Solution Approach 1:
The system changes the frequency parameter of the comparison clock by selectively using either the internal clock or the divided clock based on the external clock frequency. This parameter adaptation reduces the frequency difference between the internal clock and comparison clock, thereby improving phase locking efficiency while maintaining reliable phase locking.
Solution Approach 2:
The phase sensing unit dynamically selects the appropriate comparison clock (internal clock or divided clock) based on the external clock frequency. This dynamic selection optimizes the frequency relationship between compared clocks, improving phase locking efficiency without sacrificing locking reliability.
3Productivity
If a clock divider is used to divide the internal clock, then phase locking efficiency improves for low-frequency external clocks, but the device complexity increases due to additional clock dividing units and terminal connections
Solution Approach 1:
The clock dividing unit is designed as a universal component that can be selectively used for both high-frequency and low-frequency external clocks. The phase sensing unit determines whether to use the divided or undivided internal clock as the comparison clock, making the clock dividing unit a multi-functional element that improves efficiency only when needed without permanently increasing complexity.
Solution Approach 2:
The system dynamically activates or deactivates the clock dividing function based on the external clock frequency. The frequency sensing unit controls whether the internal clock is divided or used directly, allowing the system to optimize phase locking efficiency for low-frequency clocks while avoiding unnecessary complexity for high-frequency clocks.
4Reliability
If the phase sensing unit compares internal clock with feedback clock, then phase locking is achieved, but the adaptability to different external clock frequencies is limited
Solution Approach 1:
The phase sensing unit dynamically adapts its operation by selectively switching the comparison clock source based on the external clock frequency. For high-frequency external clocks, it compares the internal clock with the feedback clock; for low-frequency external clocks, it compares the divided clock with the feedback clock. This dynamic adaptation maintains reliable phase locking across different frequency ranges.
Solution Approach 2:
The phase sensing unit is designed as a universal component that can perform phase comparison for both high-frequency and low-frequency external clocks by switching between different comparison clocks. This multi-functional design enhances the adaptability of the phase locking system to various external clock frequencies while maintaining reliable locking.
Data Source
AI summary
A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.