Memory DLL Latency Control Using a Divided Clock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently controlling latency due to internal clock signal delays caused by internal circuits, which can lead to increased power consumption and circuit size in delay-locked loop circuits.
Innovation Solution
A method and memory device that divides a source clock signal into a lower frequency divided clock signal for input to a delay-locked loop circuit, aligns and measures the loop delay, and uses this measurement to control command path delays, reducing the size and power consumption of the delay circuit by employing a divided clock signal in both initialization and normal operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a source clock signal with high frequency is used directly in the delay-locked loop circuit, then the operational speed is improved, but the loop delay measurement precision deteriorates due to reduced operation margin
Solution Approach 1:
The patent divides the high-frequency source clock signal into a lower-frequency divided clock signal specifically for use in the delay-locked loop circuit during initialization mode. This segmentation allows the DLL to operate with sufficient timing margin for accurate loop delay measurement, while the main system can still utilize the high-frequency source clock for fast operations.
Solution Approach 2:
The divided clock signal acts as an intermediary between the source clock signal and the delay-locked loop circuit. By introducing this intermediate frequency signal, the system enables precise loop delay measurement in the DLL without requiring the full high-frequency source clock, thus resolving the measurement precision issue while maintaining operational speed capabilities.
2Speed
If the delay-locked loop circuit is designed to handle high-frequency signals directly, then the speed performance is improved, but the circuit size and power consumption increase
Solution Approach 1:
The patent segments the clock signal handling into two paths: the source clock signal path for high-speed operations and the divided clock signal path for DLL initialization and measurement. This allows the DLL circuit to be designed for lower-frequency operation with reduced complexity and smaller size, while the system overall maintains high-speed performance through the source clock path.
3Productivity
If the delay-locked loop circuit operates at high frequency, then the operational efficiency is improved, but the power consumption increases
Solution Approach 1:
The patent divides the operational modes into initialization mode using divided clock signal and normal operation mode using source clock signal. The DLL circuit operates at lower frequency during initialization for reduced power consumption, while maintaining the capability for high-frequency operation when needed for optimal performance.
Solution Approach 2:
The system periodically switches between using the divided clock signal for DLL operations and the source clock signal for main operations. This periodic action allows the DLL to perform its measurement and synchronization functions at lower power while the system achieves high operational efficiency during data processing tasks.
Data Source
AI summary
A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.