Memory DLL Fine Delay Control for Clock Phase Synchronization
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving synchronized data output with the rising and falling edges of the system clock due to internal circuit delays, necessitating an improved delay locked loop (DLL) circuit for fine adjustments in response to changing locking states.
Innovation Solution
The proposed semiconductor memory device incorporates a phase comparator, delay chain, fine delay chain, locking state detector, and fine delay controller to compare and adjust the phase of the reference clock with the feedback clock, allowing for fine adjustments in the system clock delay to maintain synchronization, even with variations in the locking state caused by external factors like power supply voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit is used to compensate for clock signal delay, then data output synchronization with system clock is improved, but the circuit complexity increases
Solution Approach 1:
The DLL circuit is divided into two independent delay chains: a normal delay chain for coarse delay adjustment and a fine delay chain for fine delay adjustment. This segmentation allows each chain to be optimized for its specific function, reducing overall circuit complexity while maintaining synchronization reliability.
Solution Approach 2:
The patent implements dynamic switching between the normal delay chain and fine delay chain based on locking state. When the DLL is locked, the fine delay chain is activated for precise adjustment; when unlocked, only the normal delay chain operates. This dynamic operation reduces complexity by enabling the fine delay chain only when necessary.
2Measurement precision
If fine delay adjustment is implemented, then phase adjustment precision is improved, but the adjustment time increases
Solution Approach 1:
The normal delay chain performs preliminary coarse delay adjustment to bring the feedback clock phase close to the reference clock phase before the fine delay chain performs precise adjustment. This preliminary action reduces the adjustment range required by the fine delay chain, thereby reducing overall adjustment time while maintaining high precision.
Solution Approach 2:
The system dynamically switches between coarse and fine adjustment modes based on locking state. During acquisition (unlocked state), the normal delay chain provides rapid coarse adjustment. Once locked, the fine delay chain takes over for precise adjustment. This dynamic switching optimizes both speed and precision at different stages.
3Reliability
If the fine delay chain operates continuously, then phase synchronization precision is maintained, but power consumption increases
Solution Approach 1:
The fine delay chain is dynamically enabled only when the DLL circuit is in a locked state, as controlled by the locking state detector. During unlocked states, the fine delay chain remains inactive. This dynamic operation maintains synchronization precision when needed while minimizing power consumption during acquisition and transient states.
Solution Approach 2:
The locking state detector automatically controls the enabling of the fine delay chain based on the current locking state, eliminating the need for external control signals. The system self-regulates power consumption by activating the fine delay chain only when the DLL is properly locked and synchronization is required.
4Speed
If the DLL circuit responds rapidly to locking state changes, then synchronization speed is improved, but stability decreases
Solution Approach 1:
The system dynamically adjusts its response characteristics based on locking state. During unlocked states, the DLL responds rapidly to achieve lock. Once locked, the response becomes more gradual and stable, preventing oscillations. This dynamic response adjustment maintains both speed and stability at different operational phases.
Solution Approach 2:
The normal delay chain performs preliminary adjustment to achieve coarse lock first, establishing a stable baseline before the fine delay chain performs precise adjustment. This preliminary action prevents direct rapid switching in the fine delay chain, thereby maintaining stability while achieving rapid overall synchronization.
Data Source
AI summary
A semiconductor memory device includes a phase comparator, a delay chain, a delay controller, a fine delay chain, a delay model, a locking state detector, and a fine delay controller. The phase comparator compares a phase of a reference clock with that of a feedback clock. The delay chain delays and outputs the reference clock. The delay controller controls a delay value of the delay chain in response to the comparison result of the phase comparator. The fine delay chain outputs a delay value of a clock outputted from the delay chain. The delay model delays a clock to a modeled delay value to provide a delayed clock as the feedback clock. The locking state detector generates a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock. The fine delay controller controls a fine adjustment value of the fine delay chain.