Memory DLL Locking Time Calibration for Stable Low-Latency Operation
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Solution Overview
Problem
Setting a target locking time for a delay locked loop in memory apparatuses is challenging due to variations in process, voltage, clock rate, and temperature, often requiring a high locking time that may be unnecessary, leading to latency issues.
Innovation Solution
A system comprising a signal generating device, a measuring device, and a computing device that tests a memory apparatus by inputting signals with varying operational parameters, measuring output signals, and determining a target locking time based on candidate operational parameters to ensure stable operation without excessive locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a high locking time is set for the delay locked loop, then stability is improved, but latency increases
Solution Approach 1:
The patent applies parameter changes by systematically varying operational parameters (process, voltage, clock rate, temperature) to determine the minimum locking time required for stable DLL operation. Instead of using a fixed high locking time, the system dynamically adjusts the locking time parameter based on measured operational conditions, thereby reducing unnecessary latency while maintaining stability.
Solution Approach 2:
The patent implements dynamics by making the locking time adaptive rather than static. The system continuously monitors operational parameters and adjusts the locking time accordingly, allowing the DLL to achieve stability with the minimum necessary locking time under varying conditions, thus optimizing both stability and latency performance.
2Reliability
If a high locking time is used to ensure stable operation, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent changes the locking time parameter from a conservative fixed value to an optimized value determined through systematic testing of operational parameters. This allows the system to maintain reliability by ensuring stable operation across process, voltage, clock rate, and temperature variations, while simultaneously improving productivity by reducing the locking time to the minimum necessary for stability.
Solution Approach 2:
The patent enables the memory apparatus to self-determine its optimal locking time through internal testing and measurement of operational parameters. The system automatically identifies the minimum locking time required for stable DLL operation under specific conditions, eliminating the need for conservative external settings and thereby improving memory performance while maintaining reliability.
3Measurement precision
If operational parameters are varied to find optimal locking time, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a testing system that can measure multiple operational parameters (process, voltage, clock rate, temperature) and determine optimal locking time across all these dimensions. The same testing apparatus handles parameter variation, measurement, and analysis, thereby achieving high measurement precision without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the functions of parameter control, signal generation, measurement, and analysis into an integrated testing system. By combining these functions, the system achieves precise determination of target locking time under varying operational conditions without the complexity overhead of separate independent systems for each function.
Data Source
AI summary
A system and a method for determining a target locking time for a delay locked loop of a memory apparatus are provided. The system includes a signal generating device, a measuring device and a computing device. The signal generating device is configured to provide a first set of input signals to the memory apparatus in accordance with a first set of first operational parameters and a set of second operational parameters. The measuring device is configured to measure a first set of output signals from the memory apparatus in response to the first set of input signals, and to determine whether the delay locked loop fails at any combination of the first set of first operational parameters and the set of second operational parameters. The computing device is configured to determine a first candidate operational parameter to further determine the target locking time based on the first candidate operational parameter.