Memory DLL Periodic Update Circuit for Low-Power Timing Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor memory devices, the delay-locked-loop (DLL) fails to update sufficiently during power-down or self-refresh modes, leading to potential malfunctions and data output issues due to insufficient update time, especially when these modes are maintained for extended periods or with changes in power.

Innovation Solution

A DLL control circuit that generates an oscillation signal with a predetermined period when in OFF states, using a pulse generating and dividing portion to create a DLL update signal, ensuring the DLL is updated with a pulse width between 5 and 20 cycles of the external clock, regardless of the clock enable signal or external commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the delay-locked-loop is turned off or enters standby state during power-down or self-refresh modes to reduce current consumption, then current consumption is reduced, but the DLL cannot perform updates sufficiently leading to malfunction

Engineering Contradiction:
Improvecurrent consumptionVSAvoidDLL update sufficiency
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements periodic update actions for the DLL during power-down and self-refresh modes. An update counter is incremented periodically, and when it reaches a predetermined threshold, the DLL is activated for an update operation. This periodic activation ensures the DLL maintains accuracy while minimizing power consumption by keeping it inactive most of the time.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent performs preliminary update actions before the DLL completely loses synchronization. By monitoring the duration of power-down modes and triggering updates at predetermined intervals, the system proactively maintains DLL accuracy rather than waiting for malfunction to occur. This preliminary action prevents timing skew accumulation that would otherwise lead to data output errors.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If the clock enable signal is maintained high for minimum pulse holding time and then low for refresh interval in self-refresh emulation mode, then current consumption is reduced, but the high interval is too short to ensure sufficient DLL update time

Engineering Contradiction:
Improvecurrent consumptionVSAvoidDLL update time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent uses the clock enable signal's high interval to perform preliminary DLL update operations before the low refresh interval begins. The update counter accumulates during the high interval, and when the threshold is reached, the DLL is activated to complete the update operation, ensuring timing accuracy is maintained despite the short duration of the high interval.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic DLL updates synchronized with the self-refresh emulation mode's clock enable signal cycles. By triggering updates at regular intervals during the high intervals and completing them during the transition to low intervals, the system ensures sufficient update time is allocated periodically without extending the overall refresh interval, thus maintaining low power consumption.

Inventive Principle:
Principle #19Periodic action

3Reliability

If the DLL is updated frequently to prevent malfunction, then reliability is improved, but current consumption increases due to prolonged high state of clock enable signal

Engineering Contradiction:
ImproveDLL functionalityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic DLL updates at predetermined intervals rather than continuous updates. The update counter increments with each clock cycle, and the DLL is activated only when the counter reaches a threshold value. This periodic approach ensures the DLL remains functional and synchronized while minimizing the duration the clock enable signal must remain high, thus reducing overall power consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent dynamically adjusts the update frequency and timing parameters based on the operational mode and accumulated skew. By changing the update interval parameters adaptively - using longer intervals during stable power-down modes and shorter intervals during transitions - the system optimizes the balance between maintaining DLL reliability and minimizing power consumption throughout different operational phases.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7414447B2Semiconductor memory device including delay-locked-loop control circuit and control method for effective current consumption management
Publication Date: 2008.08.19 SK HYNIX INC
  • US7414447B2 patent drawing
  • US7414447B2 patent drawing
  • US7414447B2 patent drawing

AI summary

A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.