Semiconductor Memory DLL with Coarse-Fine Delay Phase Generation
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in generating multiple internal clock signals with different phases to efficiently handle increased data output, as their DLL circuits are limited in phase adjustment and duty cycle correction.
Innovation Solution
A DLL circuit with a delay line comprising coarse and fine delayers, a delay control section for phase comparison and control signal generation, and a duty cycle correction section for generating internal clock signals, allowing for the production of multiple clock signals with varying phases and corrected duty ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional DLL circuit is used to provide internal clock signals, then the phase can be adjusted to match external clock signals, but the circuit cannot generate multiple internal clock signals with different phases needed for high-speed data output
Solution Approach 1:
The delay line is divided into multiple parallel delay paths, each capable of generating clock signals with different phases. This segmentation allows the DLL circuit to simultaneously produce multiple phase-shifted clock signals, enabling high-speed data output while maintaining phase adjustment capability for each path independently.
2Productivity
If multiple internal clock signals with different phases are generated to increase data output, then productivity improves, but the conventional DLL circuit lacks the adaptability to provide the required phase variations
Solution Approach 1:
The delay line structure is designed to serve multiple functions simultaneously: it provides delay adjustment for phase matching while also generating multiple clock signals with different phases for parallel data output. This multi-functionality resolves the contradiction by making the same circuit structure adaptable to both phase control and high-speed data output requirements.
3Productivity
If the operation speed of semiconductor memory apparatus is increased to output more data, then productivity increases, but the conventional DLL circuit cannot provide sufficient phase diversity for handling increased data volume
Solution Approach 1:
The invention introduces a new dimension to the clock signal generation by creating multiple parallel delay paths that operate simultaneously. This dimensional expansion from a single delay path to multiple paths enables the circuit to generate clock signals with different phases, providing the adaptability needed to handle increased data output speeds through parallel processing.
Data Source
AI summary
A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.