Memory DLL Synchronization for Low-Power Reliable Self-Refresh

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Solution Overview

Problem

Current memory devices face challenges in maximizing system performance, reducing power consumption, and enhancing reliability due to inefficiencies in clock synchronization, data integrity, and self-refresh modes, particularly in high-capacity systems where power management and environmental adaptability are critical.

Innovation Solution

The memory device incorporates a delay locked loop (DLL) that is synchronized periodically, error control coding for data integrity, and a self-refresh mode that updates the DLL during periodic wake-ups, allowing for reduced power consumption and faster exit from self-refresh, along with temperature-controlled refresh rates to optimize performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DLL is continuously synchronized, then the memory device maintains stable operation, but power consumption increases

Engineering Contradiction:
Improvestable operationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic synchronization of the DLL using the MEMcal command instead of continuous synchronization. The DLL is synchronized at specific intervals determined by a synchronization counter, which resets after a predetermined number of cycles. This periodic approach maintains operational stability while significantly reducing power consumption compared to continuous synchronization.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If self-refresh mode is used, then power consumption is reduced, but recovery time after mode exit increases

Engineering Contradiction:
Improvepower consumptionVSAvoidrecovery time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing DLL synchronization during the self-refresh mode before exiting to normal operation. The synchronization counter is reset and the DLL is synchronized in advance during self-refresh, so that when the device exits self-refresh mode, the DLL is already in a stable state. This eliminates the need for post-exit synchronization delays, reducing recovery time while maintaining the power savings of self-refresh mode.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If a fixed preamble time is used for data strobe signals, then the timing is simple, but adaptability to varying operating conditions is reduced

Engineering Contradiction:
Improvetiming simplicityVSAvoidadaptability to operating conditions
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic preamble time adjustment based on operating conditions. The data strobe signal includes a preamble period whose length is determined by a counter that increments with each data strobe cycle. The counter can be reset or modified based on system state, allowing the preamble time to adapt dynamically to varying operating conditions such as temperature, voltage, and workload, while maintaining relatively simple timing control logic.

Inventive Principle:
Principle #15Dynamics

4Reliability

If refresh operations are performed continuously, then memory reliability is maintained, but power consumption increases

Engineering Contradiction:
Improvememory reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements feedback-based refresh control by monitoring a temperature sensor and using this information to determine when refresh operations are necessary. The temperature sensor provides feedback on the memory device's thermal state, and the refresh controller uses this feedback to enable or disable refresh operations accordingly. This allows the system to maintain memory reliability through refresh operations only when temperature conditions require it, significantly reducing unnecessary power consumption while preserving reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20110055671A1Advanced memory device having improved performance, reduced power and increased reliability
Publication Date: 2011.03.03 GLOBALFOUNDRIES US INC
  • US20110055671A1 patent drawing
  • US20110055671A1 patent drawing
  • US20110055671A1 patent drawing

AI summary

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.