Memory System Dirty Line Table Bit Error Rate Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems in portable information terminals face challenges in reducing power consumption and bit error rates, particularly with magnetoresistive random access memory (MRAM) exhibiting high bit error rates compared to SRAM or DRAM.
Innovation Solution
A memory system configuration that includes a nonvolatile memory data region with a dirty line table (DLT) having a lower bit error rate than the main nonvolatile memory, which stores data before writing it back to the main memory, ensuring data reliability by using a combination of SRAM or DRAM with error detection and correction units across multiple cache levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If MRAM is used as nonvolatile memory to reduce power consumption and improve integration, then energy efficiency and cell size are improved, but bit error rate increases
Solution Approach 1:
The patent introduces a dirty line table (DLT) as an intermediary data structure between the MRAM cache and main memory. The DLT stores metadata including validity flags and address information, enabling the system to track which cache lines need to be written back. This intermediary mechanism allows the system to maintain MRAM's low power consumption while managing data integrity through software-controlled bookkeeping rather than relying solely on hardware error correction.
Solution Approach 2:
The patent segments the memory system into distinct functional components: the MRAM cache data region, the dirty line table for metadata storage, and the main memory. By segmenting the cache management function into separate data storage (MRAM) and control information storage (DLT), the system can optimize each component for its specific purpose while collectively addressing the bit error rate issue through coordinated operation.
2Loss of energy
If MRAM cache is used to replace nonvolatile memory for lower power consumption, then energy efficiency is improved, but data reliability deteriorates due to higher bit error rate
Solution Approach 1:
The patent creates a logical copy of cache line metadata in the dirty line table that mirrors the state of data in the MRAM cache. By maintaining this separate copy of control information (validity flags, addresses), the system can verify data status without directly reading from the error-prone MRAM cells, thus preserving data integrity while maintaining the energy efficiency benefits of MRAM standby power characteristics.
3Reliability
If error detection and correction units are added to improve data reliability, then bit error rate is reduced, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based error detection and correction mechanisms with a software-managed metadata tracking system. Instead of using additional error correction code (ECC) hardware circuits that would increase device complexity, the system uses simple validity flags and address tracking in the dirty line table, managed through software logic in the cache controller, to achieve comparable reliability improvements.
Data Source
AI summary
A memory system has a first memory which comprises a nonvolatile memory data region, and a second memory which stores data before storing in a third memory, the data not being written back on the third memory in a lower-level with access priority lower than access priority of the first memory, among data inside the nonvolatile memory data region, wherein the second memory has a bit error rate lower than a bit error rate of the first memory.