Semiconductor Memory Domain Crossing Margin via Phase-Shifted Latches
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Solution Overview
Problem
Conventional semiconductor memory devices have an unstable domain crossing margin due to processing procedures, temperature, and voltage levels, leading to reduced reliability and performance.
Innovation Solution
A semiconductor memory device is designed with a division unit that generates internal data strobe signals with twice the period and 90-degree phase differences, which are used by a data align unit to extend the data alignment period, increasing the domain crossing margin from the external data strobe signal to the internal clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is aligned using conventional latches with rising and falling data strobe signals, then data alignment is achieved, but the domain crossing margin is limited to ±0.5 tCK
Solution Approach 1:
The data alignment structure is segmented into multiple latch units (first latch unit, second latch unit, third latch unit, fourth latch unit) that operate in sequence. Each latch unit captures data at different phases, dividing the alignment function into discrete stages that collectively extend the domain crossing margin beyond the conventional ±0.5 tCK limitation.
Solution Approach 2:
The patent introduces dynamic phase shifting between consecutive latch units. The second latch unit receives the inverted output of the first latch unit, creating a 180-degree phase difference. This dynamic phase manipulation allows data to be captured at different temporal points, effectively extending the alignment window and domain crossing margin.
2Reliability
If the activation period of the signal synchronized with the external data strobe signal is maintained, then domain crossing is achieved, but the margin is determined by the narrow activation period width
Solution Approach 1:
The patent performs preliminary data capture in the first latch unit during the rising edge of the data strobe signal. This preliminary action prepares the data before it needs to be transferred to the next domain, allowing the activation period to start earlier and effectively extend the margin without requiring a wider activation period.
Solution Approach 2:
The inverted output signal from the first latch unit serves as an intermediary that bridges the gap between the original data signal and the next stage. This intermediary signal with 180-degree phase shift allows the system to maintain data validity beyond the original activation period, effectively extending the domain crossing margin.
3Reliability
If conventional data alignment using seven latches is used, then data is latched in response to rising and falling data strobe signals, but the domain crossing margin remains unstable under varying processing conditions
Solution Approach 1:
The patent employs dynamic phase inversion between latch units to create temporal separation in data capture. By inverting the output of the first latch unit and feeding it to the second latch unit, the system creates a phase difference that stabilizes the domain crossing margin against variations in processing conditions, temperature, and voltage.
Solution Approach 2:
The patent utilizes periodic clock signals with specific phase relationships to control the latch units. The first and second clock signals are phase-shifted versions of each other, creating a periodic action pattern that ensures data is captured at optimal moments, thereby stabilizing the domain crossing margin under varying operating conditions.
Data Source
AI summary
A semiconductor memory device with an increased domain crossing margin is provided. The semiconductor memory device includes: a data input buffer for receiving an external data in response to a driving signal; a DQS input buffer for receiving an external data strobe signal in response to the driving signal; a delay unit for delaying an output signal of the DQS input buffer by a predetermined time; a division unit for dividing an output signal of the DQS input buffer to output a plurality of internal data strobe signals; and a data align unit for aligning an output data of the delay unit in response to the corresponding internal data strobe signals to output a plurality of align data.