Memory Transaction Management via Domain Identifiers

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Solution Overview

Problem

In computing devices, memory transactions can lead to buffer resource consumption issues, causing software threads to stall due to lack of resources, resulting in delays and reduced quality of service, especially when slower traffic congests the system and blocks memory requests from other threads.

Innovation Solution

Assigning distinct domain identifiers to software threads based on their type, allowing the processor to manage memory transactions and control operations based on the number of transactions associated with each identifier, ensuring efficient resource allocation and synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If buffer resources are allocated to software threads for memory transactions, then memory access capability is improved, but buffer resource exhaustion causes threads to stall and system congestion increases

Engineering Contradiction:
Improvememory access speedVSAvoidthread stall time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent segments the buffer resources into multiple separate buffers, each dedicated to a specific software thread. This segmentation prevents one thread from consuming all buffer resources and causing other threads to stall, thereby resolving the contradiction between memory access capability and thread stall time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each software thread is assigned its own dedicated buffer with specific characteristics optimized for that thread's needs. This local quality approach ensures that each thread has guaranteed buffer resources available, preventing stalls while maintaining efficient memory access for each thread individually.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If slower memory traffic is allowed to proceed, then buffer utilization is improved, but system congestion increases and blocks memory requests from other threads

Engineering Contradiction:
Improvebuffer utilizationVSAvoidsystem throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

By segmenting buffers into thread-specific dedicated buffers, the system allows each thread to utilize its own buffer independently. This prevents slower traffic from one thread from blocking other threads, maintaining high system throughput while ensuring adequate buffer utilization for each thread.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dedicated buffer acts as an intermediary resource that isolates memory traffic from different threads. This mediation prevents congestion propagation between threads, allowing the system to maintain high productivity even when some threads have slower memory traffic patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If buffer resources are shared among software threads, then resource efficiency is improved, but slower traffic congests the system and blocks requests from other threads

Engineering Contradiction:
Improvebuffer resource efficiencyVSAvoidmemory request accessibility
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent segments the shared buffer resource into multiple dedicated buffers, one per thread. This segmentation maintains resource efficiency by ensuring each thread has guaranteed access to buffer space, while preventing any single thread's slower traffic from blocking other threads' memory requests.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each thread receives a dedicated buffer with characteristics suited to its specific needs, improving ease of operation for memory requests. This local optimization ensures that memory request accessibility is maintained for all threads regardless of the performance characteristics of other threads.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12175280B2Memory transaction management
Publication Date: 2024.12.24 QUALCOMM INC
  • US12175280B2 patent drawing
  • US12175280B2 patent drawing
  • US12175280B2 patent drawing

AI summary

A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.