Semiconductor Memory Dot-Pattern Masking for Low-Roughness Lithography
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Solution Overview
Problem
Existing semiconductor structures face challenges in ensuring pattern morphology and photolithography quality across different directions, leading to roughness issues that affect manufacturing yield and performance.
Innovation Solution
A semiconductor structure formation method involving a base with a memory region and peripheral regions, where a conductive layer is patterned using first and second dot patterns as masks to form independent conductive dot patterns, optimizing light conditions for photolithography and maintaining line patterns in peripheral regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuous line patterns are used for photolithography in active region and peripheral region, then photolithography can be performed simultaneously, but line roughness increases in certain directions affecting pattern quality
Solution Approach 1:
The patent segments the continuous line patterns into discrete dot patterns arranged in arrays. By converting line patterns to dot patterns in the memory region while maintaining line patterns in peripheral regions, the patent enables independent optimization of photolithography parameters for different regions, reducing line roughness while maintaining manufacturing efficiency.
Solution Approach 2:
The patent applies different pattern types to different regions: dot patterns are used in the memory region where high precision is needed, while line patterns are maintained in peripheral regions. This local differentiation allows each region to have optimal pattern morphology for its specific function, resolving the contradiction between overall productivity and local manufacturing precision.
2Manufacturing precision
If dot patterns are used in memory region and line patterns in peripheral region, then pattern morphology is improved, but process complexity increases
Solution Approach 1:
The patent segments the semiconductor device into memory region and peripheral region, applying different pattern types to each. This segmentation allows simplified processing in peripheral regions (using line patterns) while achieving high precision in memory regions (using dot patterns), balancing overall process complexity with pattern quality requirements.
Solution Approach 2:
The patent uses a unified photolithography process that can handle both dot patterns and line patterns within the same exposure step. The process is designed to be multi-functional, accommodating different pattern geometries without requiring separate processing steps, thereby minimizing the increase in process complexity while achieving improved pattern morphology.
Data Source
AI summary
Embodiments of the present application relate to a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes the following steps: providing a base, the base including a memory region, the memory region including a substrate, a conductive layer, and a first mask layer located on the conductive layer; patterning the first mask layer to form a plurality of first dot patterns arranged in a first array; backfilling the first mask layer to form a second mask layer covering the first mask layer; patterning the second mask layer to form a plurality of second dot patterns arranged in a second array; and etching the conductive layer by using the first dot pattern and the second dot pattern together as a mask pattern to form a plurality of independent conductive dot patterns.