Semiconductor Memory Device Double Verify Scheme
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Solution Overview
Problem
Current semiconductor memory devices face limitations in operating speed and reliability, particularly in three-dimensional structures where the integration of memory cells vertically stacked on a semiconductor substrate leads to inefficiencies in programming operations.
Innovation Solution
The method involves a double verify scheme with a two-step program pulse and bit line voltage adjustments based on threshold voltage measurements, applying a program allowable voltage or inhibit voltage to optimize the programming process, and using control logic to manage these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single verify scheme is used in three-dimensional memory devices, then the device complexity is reduced, but the programming speed and reliability deteriorate due to insufficient threshold voltage control
Solution Approach 1:
The verify operation is segmented into two distinct stages: an auxiliary verify operation using a first verify voltage and a main verify operation using a second verify voltage. This segmentation allows for progressive threshold voltage verification, improving programming reliability by catching failures at different stages while maintaining manageable complexity through structured operation separation.
Solution Approach 2:
The auxiliary verify operation is performed as a preliminary action before the main verify operation. This preliminary verification using the first verify voltage identifies and handles obvious programming failures early, allowing the main verify operation to focus on more subtle threshold voltage issues, thereby improving overall reliability without proportionally increasing complexity.
2Reliability
If multiple program loops are executed with conventional verify methods, then programming completeness is improved, but the operating time increases significantly
Solution Approach 1:
The double verify scheme implements feedback mechanisms where the results of the auxiliary verify operation inform the main verify operation, and subsequent program loops are adjusted based on verify outcomes. This feedback allows the system to adapt programming parameters and loop counts dynamically, improving programming completeness while reducing unnecessary iterations and time consumption.
Solution Approach 2:
The verify voltage levels and program loop parameters are made dynamic rather than fixed. The system adjusts the number of program loops and verify voltage levels based on real-time programming progress and threshold voltage distribution, allowing optimal balance between programming completeness and time efficiency for different memory cell states.
3Productivity
If a two-step program pulse is applied to increase threshold voltage shift, then programming speed is improved, but the threshold voltage distribution widens reducing reliability
Solution Approach 1:
The system dynamically changes verify voltage parameters (using two different verify voltages in auxiliary and main verify operations) to compensate for the widened threshold voltage distribution caused by two-step program pulses. By adjusting verify voltage levels based on programming stage and cell state, the system maintains programming speed while ensuring reliable verification across the broader voltage distribution.
4Productivity
If the number of program loops is reduced to improve speed, then operating time is reduced, but programming reliability deteriorates
Solution Approach 1:
The auxiliary verify operation serves as a preliminary filter that identifies successfully programmed cells before the main verify operation. This preliminary action allows the system to reduce the number of full program loops needed while maintaining reliability, as the auxiliary verify catches obvious successes and failures early, reducing the burden on subsequent loops.
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.