Memory Downlink Error Correction Circuit for Uncorrectable Error Detection
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Solution Overview
Problem
As memory device capacity increases, it becomes challenging to fabricate devices without defective memory cells, leading to the need for repair methods like redundant cells and error correction circuits to address errors during operations.
Innovation Solution
A memory system that includes a downlink error correction circuit, a memory error correction code generation circuit, an error injection circuit, and a memory core, which detect uncorrectable errors and inject errors to improve error detection and correction capabilities during data transfer and storage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits are used to correct errors in memory cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements nested error correction mechanisms where the downlink error correction circuit operates at the memory interface level, while the memory error correction code generation circuit operates at the storage level. This nested structure allows error correction functionality to be distributed across multiple hierarchical levels, improving reliability without requiring a single complex correction system.
Solution Approach 2:
The patent applies preliminary error correction by correcting errors during the downlink data transfer before the data is written to the memory core. The downlink error correction circuit performs error detection and correction in advance, preventing corrupted data from entering the storage array and thereby reducing the burden on subsequent error correction mechanisms.
2Reliability
If redundant memory cells are used to replace defective cells, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent creates a copy of the original data along with error correction codes during the write operation. This copied data is stored in the memory core with the original data, allowing the system to detect and correct errors without requiring physical replacement of defective memory cells. The copying approach maintains reliability while simplifying manufacturing requirements.
3Measurement precision
If error injection is performed to detect uncorrectable errors, then measurement precision of error detection is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the downlink error correction circuit continuously monitors the correction process and provides feedback about the status of error correction. When uncorrectable errors are detected, the system generates error correction codes and injects them back into the data stream for re-processing, thereby improving error detection accuracy through iterative feedback loops.
Data Source
AI summary
A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.