Memory Device Multiple DQ Maps I/O Width Adaptation
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Solution Overview
Problem
Semiconductor memory devices face challenges in supporting multiple data input-output (I/O) widths and varying system requirements, such as error sensitivity and data transfer speed, with existing technologies often requiring separate memory devices for different I/O widths and characteristics.
Innovation Solution
A memory device is designed to support multiple DQ mappings for both different and same I/O widths, utilizing circuitry that allows a single device to operate with various memory controllers, including those with four and eight DQ terminals, by implementing multiple DQ maps that accommodate different characteristics and system needs, reducing the number of components required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory devices are used for different I/O widths and system requirements, then each device can be optimized for specific characteristics, but the number of components and system complexity increases
Solution Approach 1:
The patent implements multiple DQ maps within a single memory device, allowing one device to support multiple I/O widths (e.g., x4 and x8) and different system requirements. This multi-functionality eliminates the need for separate specialized devices while maintaining optimized performance for each configuration through selectable mapping schemes.
Solution Approach 2:
The patent changes the mapping parameters between memory cells and DQ terminals by selecting different DQ maps based on system requirements. This allows the same physical device to adapt its data path configuration for different I/O widths and error correction needs without hardware changes, resolving the contradiction between specialization and component reduction.
2Adaptability or versatility
If multiple DQ mappings are supported for different I/O widths, then a single device can serve multiple products, but the internal circuitry and mapping complexity increase
Solution Approach 1:
The patent segments the data path into multiple configurable routes by implementing distinct DQ maps. Each map represents a segmented configuration for specific I/O widths, allowing the device to select the appropriate segment (mapping) based on system needs. This segmentation enables versatility while managing complexity through modular, selectable pathways rather than fully interconnected complex circuitry.
3Adaptability or versatility
If circuitry is added to support multiple DQ maps for same I/O width, then different features and characteristics can be accommodated, but the device complexity and cost increase
Solution Approach 1:
The patent makes a single memory device universal by incorporating multiple DQ maps that support different features (e.g., error correction modes, different burst lengths) for the same I/O width. This eliminates the need for multiple specialized device variants, reducing manufacturing complexity and cost while maintaining feature versatility through software or configuration-based selection of the appropriate map.
Data Source
AI summary
A memory device may support multiple DQ maps. Two or more of the DQ maps may support memory operations using a same input-output width. In some examples, one or more components for supporting a DQ map for a different input-output width may be used to also support one or more of the DQ maps for the same-input output width.