Memory DQ PAM Scaling Across Operating Frequencies
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Solution Overview
Problem
Existing memory systems face challenges in achieving high-capacity and high-speed data transmission using non-return to zero (NRZ) type encodings, which are inadequate for modern demands, particularly in mobile devices and internet-accessed systems.
Innovation Solution
The implementation of pulse amplitude modulation (PAM) methods for data (DQ) signal transmission and reception in memory devices, with scaling of DQ signals based on operating frequency conditions to improve data transmission performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-return to zero (NRZ) type encodings are used for data transmission, then the system is simple to implement, but it cannot satisfy demands for high-capacity and high-speed data transmission
Solution Approach 1:
The patent applies pulse amplitude modulation (PAM) with multiple amplitude levels (e.g., PAM4 with 4 levels) to encode multiple bits per symbol, thereby increasing data transmission capacity and speed beyond what NRZ encoding can achieve. This parameter change in modulation technique directly resolves the contradiction by enabling higher productivity through more sophisticated signal representation.
2Productivity
If PAM methods are used for high-capacity and high-speed data transmission, then data transmission performance improves, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the PAM signal parameters (amplitude levels, transition slopes, intervals) based on operating frequency conditions. At different frequency ranges, the system optimizes these parameters to achieve the required data transmission speed while minimizing power consumption. This dynamic adaptation resolves the contradiction by allowing the system to operate efficiently across varying performance requirements.
Solution Approach 2:
The system changes key signal parameters including transition slope and interval between adjacent levels based on operating frequency. By optimizing these parameters dynamically, the system achieves high data transmission speeds when needed while reducing power consumption during operation, thereby resolving the contradiction between productivity and energy use.
3Productivity
If fixed DQ signal parameters are used, then the circuit design is simple, but data transmission performance cannot be optimized for different operating frequencies
Solution Approach 1:
The patent introduces dynamic signal scaling circuits that adjust DQ signal parameters (amplitude, transition slope, interval) based on detected operating frequency conditions. This dynamic approach enables optimal data transmission performance across different frequency ranges while managing circuit complexity through systematic design of the scaling mechanism.
Solution Approach 2:
The system incorporates feedback mechanisms to detect operating frequency conditions and automatically adjust DQ signal parameters accordingly. This feedback loop ensures that the signal transmission is continuously optimized for the current operating conditions, resolving the contradiction between performance optimization and design simplicity.
Data Source
AI summary
A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.