Nonvolatile Memory Write Control via Dynamic Drain Bias
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Solution Overview
Problem
In flash memory devices, repeated write-erase cycles lead to a decrease in threshold voltage, causing off-leakage currents and deteriorating write characteristics, as the source bias writing method can result in insufficient drain-source voltage if the source potential exceeds a certain level, preventing a desired write current from flowing through selected memory cells.
Innovation Solution
A nonvolatile semiconductor memory device with a source bias control circuit and a drain bias control circuit that variably set the source and drain potentials, respectively, to maintain a sufficient drain-source voltage by correlating the source potential with the drain potential, ensuring a desired write current flows through selected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source potential is increased to suppress off-leakage currents, then the write characteristic is improved, but the drain-source voltage becomes insufficient
Solution Approach 1:
The patent applies dynamics by making the drain potential variable rather than fixed. The drain bias control circuit dynamically adjusts the drain potential based on the actual source potential level, allowing the system to adapt to changing conditions during write operations. This dynamic adjustment ensures that the drain-source voltage remains sufficient even when source potential is elevated to suppress off-leakage currents.
Solution Approach 2:
The patent changes the parameter of drain potential from a fixed value to a variable value that depends on source potential. By introducing a drain bias control circuit that monitors and adjusts drain potential based on source potential measurements, the system can maintain appropriate drain-source voltage levels across different operating conditions, resolving the contradiction between suppressing leakage and maintaining write capability.
2Reliability
If the source potential is set high to suppress off-leakage currents, then the threshold voltage effect is weakened, but the write time increases
Solution Approach 1:
The patent changes the drain potential parameter dynamically based on source potential conditions. When source potential is high (for leakage suppression), the drain bias control circuit adjusts drain potential accordingly to maintain sufficient drain-source voltage, enabling faster write operations. This parameter adaptation reduces write time overhead while maintaining reliable leakage suppression.
3Duration of action of stationary object
If repeated write-erase cycles are performed, then the memory device maintains functionality, but the threshold voltage decreases further
Solution Approach 1:
The patent implements feedback by having the drain bias control circuit monitor the actual source potential and adjust drain potential accordingly. This feedback mechanism compensates for threshold voltage degradation from repeated write-erase cycles, maintaining reliable write operations throughout the memory device's lifespan by adapting to changing electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents write failures by securing a sufficient drain-source voltage, even when the source potential is set high to suppress off-leakage currents, thereby maintaining excellent write characteristics and reducing write time overhead.
Implementation Method 1
The present invention relates to a nonvolatile semiconductor memory device having memory cells of field effect transistor type
Data Source
AI summary
A nonvolatile semiconductor memory device in accordance with the present invention is provided with a plurality of memory cells of field effect transistor type, a source bias control circuit, and a drain bias control circuit. The source bias control circuit variably sets the potential of a source line connected in common to the sources of the plurality of memory cells at the time of write operation. The drain bias control circuit variably sets the potential of the drains of the plurality of memory cells at the time of write operation according to the potential of the source line.