Semiconductor Memory Device Voltage Configuration for Drain Disturb
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining data retention characteristics and mitigating disturb stress during operations, which can lead to data breakage, necessitating improved reliability and reduced leakage current.
Innovation Solution
The semiconductor memory device incorporates a structure with multiple n-wells and p-channel memory transistors, where specific voltage configurations are applied to bit lines, n-wells, and word lines to suppress drain disturb and leakage current, including applying different voltages to selected and unselected memory cells to control electron injection and extraction efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage configuration is applied during programming, then programming operation can be performed, but drain disturb and leakage current increase, degrading data retention characteristics
Solution Approach 1:
The patent applies different voltage levels to different n-wells based on their selection state. Selected n-wells receive a first voltage level during programming, while unselected n-wells receive a second voltage level that is lower than the first. This local differentiation suppresses drain disturb and leakage current in unselected memory cells, thereby improving data retention characteristics without compromising programming operation.
2Reliability
If higher voltage is applied to suppress leakage current, then data retention improves, but power consumption increases
Solution Approach 1:
The patent dynamically changes the voltage parameter applied to n-wells based on their selection state. During programming, selected n-wells are maintained at a higher voltage level to enable proper programming operation, while unselected n-wells are switched to a lower voltage level to suppress leakage current and reduce power consumption. This selective parameter change achieves both data retention improvement and power efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces drain disturb and leakage current, enhancing the reliability and data retention of semiconductor memory devices while minimizing power consumption.
Implementation Method 1
applying different voltages to selected and unselected memory cells to control electron injection and extraction efficiently
Implementation Method 2
specific voltage configurations are applied to bit lines, n-wells, and word lines to suppress drain disturb and leakage current
Data Source
AI summary
Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor, a first voltage is applied to the first bit line, a second voltage is applied to the first n-well, and a third voltage lower than the second voltage is applied to the second n-well.