3D Memory Word Line Driver Layout With Selective Dielectric Spacing
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in optimizing the layout of word line driver transistors to reduce footprint and improve electrical connectivity while maintaining effective isolation between memory blocks.
Innovation Solution
A compact word line driver transistor layout is implemented, where neighboring pairs of output nodes are laterally spaced by different widths of dielectric isolation structures based on the connectivity of word lines within the same or different memory blocks, allowing for reduced lateral dimensions and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If word line driver transistors are arranged with uniform lateral spacing, then manufacturing is simplified, but device area is increased and electrical connectivity efficiency is reduced
Solution Approach 1:
The patent applies local quality by implementing non-uniform lateral spacing of word line driver transistors based on their specific connectivity requirements. Transistors driving word lines within the same memory block are positioned closer together, while those driving word lines in different memory blocks are spaced farther apart. This localized optimization reduces the overall circuit area while maintaining manufacturing feasibility through systematic placement rules.
2Reliability
If dielectric isolation structures are widened between all transistor pairs, then electrical isolation between memory blocks is improved, but device area and wiring extent are increased
Solution Approach 1:
The patent implements local quality in dielectric isolation by varying the lateral width of dielectric structures between transistor pairs based on their connectivity. Pairs of transistors driving word lines in different memory blocks are separated by wider dielectric isolation to ensure electrical isolation, while transistors driving word lines within the same memory block use narrower isolation. This selective approach maintains reliable electrical isolation where needed while minimizing overall device area.
3Area of stationary object
If word line driver transistors are closely spaced to reduce area, then device compactness is improved, but electrical isolation between memory blocks may be compromised
Solution Approach 1:
The patent resolves this contradiction by applying local quality to the spacing and isolation design. Transistors are closely spaced where connectivity allows (within the same memory block), while wider spacing with enhanced dielectric isolation is implemented where electrical separation is required (different memory blocks). This creates an optimized layout that achieves compactness without compromising isolation reliability.
Solution Approach 2:
The patent uses segmentation by dividing the word line driver circuit into groups based on memory block connectivity. Transistors are organized into segments that drive specific memory blocks, with enhanced isolation between segments. This segmentation allows close spacing within segments while maintaining isolation between segments, achieving both compactness and reliability.
Data Source
AI summary
A memory device includes memory blocks and a word line driver circuit including word line driver transistor pairs. Each of the memory blocks includes word line subblocks. Each of the word line driver transistor pairs includes a respective first word line driver transistor and a respective second word line driver transistor that share a common input node and having different respective first and second output nodes. A first subset of neighboring pairs of output nodes that are laterally spaced by a first portion of the dielectric isolation structure having a first width are electrically connected to word line zones within a same word line subblock, and a second subset of the neighboring pairs of output nodes that are laterally spaced by a second portion of the dielectric isolation structure having a second width greater than the first width are electrically connected to word lines within different word line subblocks.