Memory Output Driver Control Using DLL Lock Feedback
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Solution Overview
Problem
In conventional synchronous semiconductor memory devices, the operational state of the output driver is determined by the output driver controller rather than the state of the DLL circuit, leading to unclear data output timing.
Innovation Solution
An output driver controller that only enables the output driver after receiving a signal from the DLL circuit indicating that the internal clock is stabilized, using a counter to ensure the internal clock is locked and utilizing a reset section to manage power-down and self-refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the output driver controller determines the operational state of the output driver independently of the DLL circuit state, then the output driver can be controlled without waiting for DLL stabilization, but the data output timing becomes unclear and may be premature
Solution Approach 1:
The output driver controller receives feedback from the DLL circuit about the stabilization state of the internal clock. The DLL circuit outputs a control signal indicating whether the internal clock is locked and stabilized, and the output driver controller uses this feedback to determine when to enable the output driver, ensuring data output timing accuracy while maintaining productivity
Solution Approach 2:
The DLL circuit performs preliminary stabilization of the internal clock before the output driver is enabled. The controller waits for the DLL to generate a stabilization control signal before activating the output driver, ensuring that data output operations only begin when the clock is ready, thus preventing premature enabling while maintaining system efficiency
2Loss of time
If the output driver is enabled immediately without checking DLL clock stability, then the device responds faster to read commands, but data output timing becomes uncertain and may cause timing errors
Solution Approach 1:
The system uses feedback from the DLL circuit's stabilization status to control the output driver timing. The DLL circuit monitors its own clock stabilization state and provides this information to the output driver controller, which then precisely determines when to enable data output, ensuring both fast response and high timing precision
Solution Approach 2:
A control signal from the DLL circuit acts as an intermediary between the clock generation process and the output driver control. This intermediary signal carries information about clock stabilization status, allowing the output driver controller to make informed timing decisions that balance response speed with timing precision
Data Source
AI summary
A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for controlling operation of the output driver, wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.