Memory Driving Circuit with Auxiliary Edge Boost for Faster Rise Time
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Solution Overview
Problem
Existing driving circuits in memory devices face limitations in meeting the increasing demand for faster data transmission and read/write speeds due to constraints in power consumption and rise time of signal transitions, which can result in transmission errors and reduced timing margins.
Innovation Solution
A driving circuit comprising a primary driver and an auxiliary driver, where the primary driver enhances the driving capability of the signal, and the auxiliary driver shortens the rise time of the output signal through an auxiliary driving signal, aided by a second pull-up transistor and an edge enhancement circuit, which generates an edge enhancement signal to control the ON/OFF of the transistor, thereby improving the timing margin and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single driver is used to enhance driving capability, then the signal transmission strength is improved, but the rise time of the output signal becomes too long, causing transmission errors
Solution Approach 1:
The driving circuit is segmented into a primary driver and an auxiliary driver. The primary driver enhances the driving capability of the first signal to generate a second signal with greater driving capability, while the auxiliary driver generates an auxiliary driving signal to shorten the rise time of the second signal. This segmentation allows each component to specialize in one function, resolving the contradiction between driving capability and rise time.
Solution Approach 2:
The patent merges the primary driver and auxiliary driver into a unified driving circuit that works together. The auxiliary driver is connected to the output terminal of the primary driver, and their signals are combined to produce the final output signal. This merging allows the circuit to simultaneously achieve enhanced driving capability and reduced rise time, which neither component could achieve alone.
2Loss of time
If the rise time is reduced to meet faster data transmission, then the timing margin is improved, but the power consumption increases
Solution Approach 1:
The auxiliary driver is activated only during the critical transition periods when rise time needs to be shortened, rather than continuously. The edge enhancement circuit detects the edges of the first signal and triggers the auxiliary driver accordingly. This partial action approach reduces power consumption compared to keeping the auxiliary driver always on, while still achieving the required rise time reduction.
Solution Approach 2:
The edge enhancement circuit automatically detects signal edges and controls the activation of the auxiliary driver without external intervention. The circuit self-regulates its power consumption by activating the auxiliary driver only when needed for edge enhancement, thereby reducing overall power consumption while maintaining performance requirements.
3Productivity
If the driving capability is enhanced to meet higher data rates, then the transmission speed is improved, but the signal integrity deteriorates due to transmission errors
Solution Approach 1:
The auxiliary driver acts as an intermediary between the primary driver and the output. It receives the second signal from the primary driver and adds an auxiliary driving signal to enhance the edges. This intermediary function ensures that the signal maintains its integrity during high-speed transmission by compensating for signal degradation, thereby improving both transmission speed and signal integrity.
Data Source
AI summary
A driving circuit includes: a primary driver configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driver connected to an output terminal of the primary driver and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.