3D Memory Word Line Driver Layout for Latch-Up Suppression
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Solution Overview
Problem
The existing 3D memory devices face challenges in scaling due to the limited area for forming word line (WL) drivers, which increases well resistance and leads to latch up issues, primarily because of the close arrangement of p-well and n-well structures required by design rules.
Innovation Solution
The solution involves spacing apart the p-well and n-well structures, allowing same-type transistors to share a well, reducing the total area required for WL drivers and increasing well width, thereby reducing latch up issues and allowing for more compact and efficient arrangement of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If p-well and n-well structures are arranged closely to reduce area, then area is reduced, but well resistance increases and latch up issues occur
Solution Approach 1:
Transistors of the same type from different word line drivers are merged into shared wells. Specifically, first transistors from multiple WL drivers share a first well, and second transistors from multiple WL drivers share a second well. This merging reduces the total number of wells needed, allowing closer spacing without increasing well resistance, thereby resolving the contradiction between area reduction and reliability.
Solution Approach 2:
The shared wells serve multiple functions by accommodating transistors from multiple different word line drivers. A single well structure supports multiple transistors that belong to different WL drivers, making the well structure universal rather than dedicated to a single driver. This multi-functionality enables area reduction while maintaining sufficient well width for reliable operation.
2Reliability
If p-well and n-well structures are spaced apart to reduce latch up issues, then reliability is improved, but area increases
Solution Approach 1:
By merging same-type transistors from multiple WL drivers into shared wells, the patent reduces the total well count. This allows the wells to be spaced closer together while maintaining adequate width within each well for latch-up suppression. The merging strategy enables compact arrangement without sacrificing reliability.
3Reliability
If well width is increased to reduce latch up issues, then reliability is improved, but area increases
Solution Approach 1:
The patent merges same-type transistors from multiple WL drivers into shared wells, which allows each well to be sufficiently wide for latch-up suppression while reducing the total number of wells. This merging approach achieves wide wells without proportionally increasing total area, as multiple transistors share the same well structure.
Solution Approach 2:
Each shared well serves multiple transistors from different WL drivers, making the well structure universal. This multi-functionality allows the well width to be optimized for reliability without requiring a separate well for each transistor, thereby avoiding proportional area increase.
Data Source
AI summary
A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.