Semiconductor Memory Driver Dual-Stage Precharge Circuit

Solution Overview

Problem

Current semiconductor memory devices face issues with power noise and instability due to high current consumption during read/write operations, particularly because of the drastic voltage changes in data lines, which can lead to potential damage and decreased stability.

Innovation Solution

A semiconductor memory device with a driver that includes a driving block and precharge units capable of precharging signal lines with different driving powers during distinct precharge operations, ensuring stable data signal line precharge operations by using a first precharge unit for initial precharge with a weak power and a second precharge unit for subsequent precharge with a stronger power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If precharge operation is performed with high driving power, then precharge speed is improved, but current consumption increases causing power noise and instability

Engineering Contradiction:

Improveprecharge speedVSAvoidstability of data lines

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The precharge operation is divided into two distinct phases: a first precharge operation with first driving power and a second precharge operation with second driving power. This segmentation allows the system to perform precharging in stages, reducing the impact of high current consumption while maintaining precharge functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements periodic precharge operations with alternating driving powers. The first precharge operation uses first driving power followed by a second precharge operation with second driving power, creating a periodic pattern that balances speed requirements with stability requirements.

Inventive Principle:

Principle #19Periodic action

2Loss of energy

If precharge operation is performed with low driving power, then current consumption is reduced, but precharge speed decreases

Engineering Contradiction:

Improvecurrent consumptionVSAvoidprecharge speed

Core Design Contradiction:

Loss of energyVSSpeed

Solution Approach 1:

The precharge operation is divided into two distinct phases: a first precharge operation with first driving power and a second precharge operation with second driving power. This segmentation allows the system to perform precharging in stages, reducing the impact of high current consumption while maintaining precharge functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the driving power parameter between the two precharge operations. The first precharge operation uses first driving power and the second precharge operation uses second driving power, allowing optimization of current consumption while maintaining acceptable precharge speed through the combined effect of both operations.

Inventive Principle:

Principle #35Parameter changes

3Speed

If voltage level of data lines changes drastically, then data transfer speed is improved, but power noise and unwanted effects increase

Engineering Contradiction:

Improvedata transfer speedVSAvoidpower noise

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The voltage change process is segmented into two stages through two precharge operations with different driving powers. This segmentation prevents drastic voltage changes by distributing the voltage transition over time, thereby reducing power noise while still achieving the required data transfer speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements periodic precharge operations with alternating driving powers. The first precharge operation uses first driving power followed by a second precharge operation with second driving power, creating a periodic pattern that balances speed requirements with stability requirements.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9455003B2Driver and semiconductor memory device including the same

Publication Date: 2016.09.27 MIMIRIP LLC

AI summary

A driver includes a driving block suitable for driving a data transferred through a first signal line to a second signal line, a first precharge unit suitable for precharging the second signal line with a first driving power during a first precharge operation; and a second precharge unit suitable for precharging the second signal line with a second driving power which is different from the first driving power during a second precharge operation performed subsequent to the first precharge operation.