Semiconductor Memory Driver Calibrating Spike Current for Write Speed
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Solution Overview
Problem
Next-generation semiconductor memories, such as PRAM and ReRAM, face write speed reductions due to parasitic capacitance, leading to errors in data writing when memory cells at different distances receive varying spike currents.
Innovation Solution
A driver for semiconductor memory that adjusts the height and width of the spike current supplied to memory cells using a momentarily dropping voltage generation unit, D/A conversion unit, cell voltage detection unit, and calibration control unit to ensure consistent charge delivery across memory cells, reducing errors in data writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional current driving method is used to supply write current to memory cells, then the write operation can be performed, but write delay occurs due to parasitic capacitance in cells and wiring, reducing write speed
Solution Approach 1:
The patent applies preliminary action by pre-charging parasitic capacitance with a spike current before the actual write operation. The spike current is supplied in advance to charge the parasitic capacitance of cells and wiring, so that when the write current is applied, the charging delay is already minimized, enabling faster write operations.
Solution Approach 2:
The patent uses periodic action by applying a momentary spike current pulse before the write operation. This periodic pulse is generated at specific timing intervals to charge the parasitic capacitance, creating a rhythmic charging pattern that optimizes the write speed by preparing the circuit state periodically.
2Speed
If the spike current magnitude is increased to charge parasitic capacitance faster, then write speed increases, but error in writing data occurs when memory cells at different distances receive varying spike currents
Solution Approach 1:
The patent applies local quality by adjusting the spike current magnitude based on the distance of each memory cell from the driver. Cells at different distances receive different spike current levels - cells farther away receive larger spike currents to compensate for higher parasitic capacitance, while closer cells receive smaller spike currents, ensuring uniform charge delivery across all cells.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the spike current magnitude as a variable parameter based on cell distance. The driver changes the spike current parameter adaptively - increasing it for distant cells and decreasing it for close cells - to maintain consistent charging effect and eliminate write errors.
3Speed
If a boost circuit is used to supply spike current with magnitude adjusted according to distance from the constant current source circuit, then write speed increases, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the spike current generation function into the existing constant current source circuit. The boost circuit is combined with the constant current source to form a unified driver that can supply both the steady write current and the momentary spike current, reducing the need for separate dedicated spike current generation circuits.
Solution Approach 2:
The patent applies universality by designing the constant current source circuit to perform multiple functions - it serves as both the write current source and the spike current generator. The circuit is configured to switch between providing steady write current and generating momentary spike currents, eliminating the need for separate specialized circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The driver effectively reduces errors in data writing by calibrating the overdrive current's height and width, ensuring consistent charge delivery to memory cells, thereby enhancing write speed and accuracy.
Implementation Method 1
a D/A conversion unit configured to output a spike current including the overdrive current using the momentarily dropping voltage
Implementation Method 2
calibrating the height and width of the overdrive current, ensuring consistent charge delivery to memory cells
Data Source
AI summary
A driver for a semiconductor memory may reduce an error in writing data in memory cells by adjusting the height and width of a spike current, when the memory cells in which data having the same level are written are arranged at different distances. In addition, the driver may reduce the error by controlling the amount of charges supplied to each of the memory cells that are arranged at different distances.