Dual DLL Circuit for Fast Memory Clock Frequency Switching
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing internal clock signals with external clock signals efficiently, particularly when the frequency changes from low to high or high to low, leading to longer synchronization times and reduced operational speed.
Innovation Solution
A delay-locked-loop (DLL) circuit is designed with two DLLs, one for low-frequency and one for high-frequency external clock signals, which store locking information beforehand and generate synchronized internal clock signals using this information, allowing for faster synchronization and higher operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single DLL circuit is used to synchronize internal clock signals with external clock signals across all frequency ranges, then the device complexity is reduced, but the synchronization time increases when frequency changes occur
Solution Approach 1:
The DLL circuit is divided into multiple specialized sub-circuits: a first DLL for low-frequency external clock signals and a second DLL for high-frequency external clock signals. Each DLL is optimized for its specific frequency range, enabling faster synchronization when frequency changes occur by switching between the appropriate DLL rather than relying on a single general-purpose DLL.
Solution Approach 2:
The system dynamically selects which DLL to use based on the frequency of the external clock signal. A frequency detection mechanism monitors the external clock frequency and switches between the first DLL (low-frequency optimized) and the second DLL (high-frequency optimized), allowing the system to adapt its synchronization mechanism to current operating conditions and minimize synchronization time during frequency transitions.
2Productivity
If a DLL circuit is designed for high-speed operation, then the operational speed increases, but the ability to handle frequency changes from low to high or high to low deteriorates
Solution Approach 1:
The DLL system is segmented into frequency-specific modules: a first DLL optimized for low-frequency operation and a second DLL optimized for high-frequency operation. This segmentation allows each module to be independently optimized for its target frequency range, maintaining high operational speed within each range while improving overall adaptability to frequency changes through selective switching between modules.
Solution Approach 2:
The DLL system achieves multi-functionality by incorporating both low-frequency and high-frequency optimized DLLs within a single circuit. The system can universally handle various frequency ranges by selecting the appropriate DLL based on the external clock frequency, thereby maintaining both high operational speed and broad frequency adaptability.
Data Source
AI summary
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.