Memory System Dual ECC Latency Reduction
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Solution Overview
Problem
The increasing capacity of memory devices has made it difficult to fabricate memory devices with no defective cells, leading to the need for error correction methods to address errors in memory systems, which currently result in significant latency during the correction process.
Innovation Solution
A memory system incorporating a memory controller, error correction circuits, and ECC generation circuits that transmit and correct data using multiple ECCs, allowing for reduced latency and enhanced error correction efficiency by differentiating between error correction methods based on error presence and type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed using traditional ECC methods, then data integrity is improved, but latency increases significantly
Solution Approach 1:
The patent segments the error correction process into two distinct phases: a fast first ECC correction phase that handles common single-bit errors quickly, and a second ECC generation phase that provides enhanced correction capability for more complex errors. This segmentation allows the system to achieve high data integrity while minimizing latency by using the faster first ECC for most cases.
Solution Approach 2:
The patent applies preliminary action by generating and applying the first ECC correction before proceeding to more complex error correction methods. The first ECC is prepared and applied in advance, allowing the system to correct most errors immediately without waiting for slower second ECC generation, thus reducing overall latency while maintaining reliability.
2Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the probability of defective cells increases
Solution Approach 1:
The patent transitions from a single-layer ECC approach to a two-layer ECC architecture. The first ECC provides basic correction capability, while the second ECC adds an additional dimension of error correction capability. This dimensional change allows the system to handle higher memory capacities with increased defective cell probability while maintaining data integrity.
Solution Approach 2:
The patent implements beforehand cushioning by generating the second ECC based on the first corrected data, creating a buffer against undetected errors. This preliminary cushioning layer ensures that even if the first ECC fails to correct certain error patterns, the second ECC provides additional protection, allowing higher capacity devices to maintain reliability.
Data Source
AI summary
A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.