Memory Device Dual-Edge Address Sampling for Concurrent Bank Access
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Solution Overview
Problem
Conventional memory devices are limited in their ability to access multiple memory banks simultaneously due to their reliance on unidirectional data ports and single-edge clock signal operations, which restricts their high transaction rate capabilities.
Innovation Solution
The implementation of memory devices with bidirectional or unidirectional data ports that receive address values on both rising and falling edges of a timing signal, allowing for simultaneous access to multiple banks using multiple address ports and data ports, enabling efficient read and write operations across different banks within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory devices use unidirectional data ports and single-edge clock operations, then device complexity is reduced, but transaction rate and access speed deteriorate
Solution Approach 1:
The data ports are designed to be bidirectional, allowing them to function as both read ports and write ports. This multi-functionality enables the memory device to perform multiple operations through the same physical interface, increasing transaction rate without proportionally increasing device complexity
Solution Approach 2:
The memory device utilizes both rising edge and falling edge of the clock signal for address sampling. By performing operations periodically on both edges of the clock cycle, the device effectively doubles the number of operations that can be performed per unit time, thereby increasing productivity
2Speed
If memory devices access multiple banks simultaneously using multiple address ports, then access speed improves, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent banks, each capable of being accessed independently. This segmentation allows simultaneous access to multiple banks through different address ports, improving access speed while keeping each bank's internal structure relatively simple
Solution Approach 2:
Multiple address ports share the same physical interface structure and control logic. Each port can independently address different banks, allowing the device to handle multiple simultaneous access requests without requiring completely separate processing paths for each port
3Loss of time
If conventional memory devices use single address port with single-edge clock, then ease of operation is maintained, but response time worsens
Solution Approach 1:
The memory device samples addresses on both rising edge and falling edge of the clock signal. This double-edge sampling effectively halves the response time for address recognition and operation initiation, improving speed while maintaining straightforward clocked operation
Solution Approach 2:
Addresses are latched and prepared in advance on both clock edges, allowing the memory device to have multiple operations in flight simultaneously. This preliminary preparation reduces the apparent response time for each individual operation while keeping the control interface simple
Data Source
AI summary
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.