Memory System Dual Interface Architecture
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Solution Overview
Problem
Current memory systems face challenges in optimizing the performance and efficiency of both volatile main memory devices and nonvolatile storage devices, as they often require different interfaces and lack direct communication pathways, leading to inefficiencies in data access and operation.
Innovation Solution
A memory system architecture that includes a processor with separate memory and storage controllers, allowing direct communication between volatile main memory and nonvolatile storage devices through a dedicated interface, enabling efficient data exchange and optimized operation by dividing memory into distinct areas accessible via different channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate interfaces are used for memory device and storage device, then compatibility with existing systems is maintained, but communication efficiency between memory and storage deteriorates
Solution Approach 1:
The memory device is divided into two distinct memory areas: a first memory area accessible through a first interface circuit (maintaining existing DRAM interface compatibility) and a second memory area accessible through a second interface circuit (enabling efficient storage device communication). This segmentation allows different interface protocols to access different portions of the same physical memory device, resolving the contradiction between interface compatibility and communication efficiency.
Solution Approach 2:
The memory device serves multiple functions by implementing both a first interface circuit (for processor communication using existing DRAM interfaces) and a second interface circuit (for storage device communication using new efficient interfaces). This multi-functionality enables the single memory device to maintain backward compatibility while simultaneously enabling high-efficiency storage communication.
2Speed
If direct communication pathway is added between memory and storage devices, then operation speed improves, but system complexity increases
Solution Approach 1:
The patent merges the memory device and storage device into a single integrated system where the memory device contains both a first interface circuit for processor communication and a second interface circuit for storage device communication. This consolidation creates a direct communication pathway between memory and storage functions within a single device, improving operation speed while managing system complexity through integration rather than adding separate independent components.
3Productivity
If new interface is implemented for storage device communication, then communication efficiency improves, but compatibility with existing processors deteriorates
Solution Approach 1:
The memory device is segmented into two accessible areas: the first memory area maintains compatibility with existing processors through the first interface circuit using standard DRAM interfaces, while the second memory area enables efficient storage communication through the second interface circuit. This segmentation allows the system to adopt new efficient interfaces for storage communication without sacrificing compatibility with existing processors.
Solution Approach 2:
The memory device acts as an intermediary between the processor and storage device. The first interface circuit maintains compatibility with existing processors, while the second interface circuit enables efficient communication with storage devices. The memory device mediates between these two interface requirements, allowing processors to continue using existing interfaces while benefiting from efficient storage communication through the alternative interface path.
Data Source
AI summary
A memory system according to example embodiments of the inventive concept may include a storage device and a memory device. The storage device includes a first interface circuit configured to be connected to a processor and a second interface circuit different from the first interface circuit. The memory device includes a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be different from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area. The first memory area is accessed by the processor through the third interface circuit and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.