Memory Cell Structure With Dual Tunneling Oxide Thickness
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Solution Overview
Problem
Current memory structures face challenges in improving the operation speed of digital memory and data retention capability of analog memory, as the tunneling dielectric layers for both types are formed by the same process and have the same thickness.
Innovation Solution
A memory structure is designed with a first and second tunneling dielectric layer, where the second tunneling dielectric layer has a greater thickness than the first, allowing for improved operation speed in digital memory and enhanced data retention in analog memory, achieved through a manufacturing method involving ion implantation and thermal oxidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same thickness tunneling dielectric layer is used for both digital and analog memory, then the manufacturing process is simplified, but the operation speed of digital memory and data retention capability of analog memory cannot be simultaneously optimized
Solution Approach 1:
The patent applies local quality by forming different thickness tunneling dielectric layers in different regions: a first tunneling dielectric layer with first thickness for digital memory cells and a second tunneling dielectric layer with second thickness for analog memory cells. This allows each region to have optimized properties for its specific function while using a unified manufacturing process that deposits material simultaneously across the substrate, with thickness controlled by local exposure to oxygen plasma treatment.
2Speed
If the tunneling dielectric layer thickness is reduced to improve digital memory operation speed, then the data retention capability of analog memory deteriorates
Solution Approach 1:
The patent resolves this contradiction by creating local quality differences in tunneling dielectric layer thickness. Digital memory cells use thinner tunneling dielectric layers (first thickness) to enable faster charge tunneling and improve operation speed, while analog memory cells use thicker tunneling dielectric layers (second thickness) to provide better charge retention and improve data retention capability. The thickness difference is achieved through selective oxygen plasma exposure after uniform deposition.
3Speed
If different thickness tunneling dielectric layers are formed for digital and analog memory, then the operation speed and data retention capability are optimized, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple functions into a unified manufacturing process. The same deposition process forms tunneling dielectric layers across the entire substrate, and the same oxygen plasma treatment process selectively thins regions. By combining these steps and using the existing memory cell structure (present or absent) as the basis for selective plasma exposure, the patent achieves different thickness layers without adding significant process complexity or requiring additional masks.
Solution Approach 2:
The manufacturing process uses self-service by allowing the existing memory cell structure to define the plasma exposure regions. Where memory cell structures are present, they protect underlying regions from plasma thinning; where they are absent, plasma thinning occurs selectively. This self-defining approach eliminates the need for additional photolithography masks and aligns the process with the existing fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory structure enhances the programming and erasing speed of digital memory while improving data retention in analog memory by varying the thickness of the tunneling dielectric layers.
Implementation Method 1
tunneling dielectric layer...located between the gate and the doped region...first charge storage layer is located between the first dielectric layer and the first tunneling dielectric layer
Data Source
AI summary
A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.