Memory ECC Architecture Using Dual Syndromes for Read Correction
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Solution Overview
Problem
As memory capacity increases, it becomes challenging to fabricate error-free memory systems, and existing error correction methods in semiconductor memory systems are inefficient, particularly in detecting and correcting errors during read and write operations.
Innovation Solution
A memory system that includes a memory controller and memory with error correction code generation circuits, generating multiple error correction codes to improve error detection and correction efficiency, where the memory controller generates system error correction codes and the memory generates memory error correction codes, enabling effective error correction during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but error-free fabrication becomes more difficult and error rate increases
Solution Approach 1:
The patent applies preliminary action by generating error correction codes during the write operation before data is stored in the memory. The memory controller generates a first system error correction code based on the write data, and the memory generates a second error correction code based on the write data and the first error correction code. This preliminary error correction preparation ensures that errors can be corrected during read operations without requiring re-fabrication of the memory.
2Reliability
If existing error correction methods are used, then error detection and correction is possible, but correction efficiency is insufficient
Solution Approach 1:
The patent segments the error correction process into two distinct phases: a first error correction code generated by the memory controller based on write data, and a second error correction code generated by the memory based on the write data and the first error correction code. This segmentation allows each code to target specific error sources, improving overall correction efficiency. During read operations, the segmented correction codes are applied systematically to correct errors in the read data.
Solution Approach 2:
The patent performs preliminary error correction preparation during the write operation by generating both the first system error correction code and the second error correction code before data is stored. This preliminary action ensures that when read operations occur, the error correction can be executed efficiently using the pre-generated codes, rather than requiring complex real-time analysis during reading.
Data Source
AI summary
A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.