Semiconductor Memory Device Dual Write Mode Voltage Optimization
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in optimizing programming voltage for memory cell transistors, leading to increased processing time and reduced processing capability, especially in three-dimensional stacked NAND flash memory where cell sizes differ, requiring repetitive programming and verification loops to reach target threshold voltages.
Innovation Solution
The implementation of a dual write mode system, including a sampling mode and a normal mode, where the sampling mode applies a higher programming voltage and adjusts based on verification loop counts to optimize the programming voltage, reducing the number of programming iterations needed to reach the target threshold voltage, and storing the optimized voltage for subsequent normal mode operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single programming voltage is used for all memory cell transistors, then the device complexity is reduced, but the manufacturing precision deteriorates because cell sizes differ in three-dimensional stacked NAND flash memory
Solution Approach 1:
The patent segments the programming voltage control into two distinct modes: sampling mode with a first programming voltage and normal mode with a second programming voltage. This segmentation allows different voltage levels to be applied based on the specific programming stage, thereby achieving both simplified control structure and high programming precision for memory cells with varying sizes in three-dimensional stacked NAND flash memory.
Solution Approach 2:
The patent changes the programming voltage parameter dynamically between two modes: sampling mode uses a first programming voltage optimized for initial threshold voltage setting, while normal mode uses a second programming voltage optimized for fine-tuning. This parameter change enables adaptation to different programming requirements, resolving the contradiction between device complexity and manufacturing precision.
2Manufacturing precision
If multiple programming and verification loops are executed to optimize programming voltage for different cell sizes, then the manufacturing precision is improved, but the processing time increases
Solution Approach 1:
The patent implements preliminary action by executing sampling mode programming first to establish an initial threshold voltage using a first programming voltage. This preliminary programming step prepares the memory cells for subsequent normal mode programming, reducing the number of verification loops needed and thereby decreasing total processing time while maintaining programming precision.
Solution Approach 2:
The patent employs periodic action by alternating between sampling mode and normal mode programming in distinct phases. The sampling mode performs initial programming with a first programming voltage, followed by normal mode programming with a second programming voltage. This periodic switching between modes optimizes the programming process by reducing redundant verification loops and minimizing processing time.
3Speed
If a higher programming voltage is applied in sampling mode, then the speed of threshold voltage establishment is improved, but the energy consumption increases
Solution Approach 1:
The patent applies dynamics by making the programming voltage adjustable between two modes: sampling mode uses a higher first programming voltage for fast initial threshold voltage establishment, while normal mode uses a lower second programming voltage for energy-efficient fine-tuning. This dynamic voltage adjustment optimizes both programming speed and energy consumption by matching voltage levels to programming requirements.
Solution Approach 2:
The patent uses partial or excessive action in sampling mode by applying a higher first programming voltage than normally required, which quickly establishes the threshold voltage in the initial programming phase. This excessive voltage application is limited to the sampling mode only, while normal mode uses a moderate second programming voltage, thereby achieving fast initial programming without excessive overall energy consumption.
Data Source
AI summary
A semiconductor memory device includes a memory cell array having a plurality of memory cell groups, the memory cell groups including a first memory group including first memory cells, and a control circuit configured to execute a first write operation targeting the first memory cells in a first mode in which the control circuit executes at least a first programming operation on the first memory cells followed by a multiple number of first verification operations to verify the first programming operation, and then in a second mode, in which the control circuit executes a second programming operation on the first memory cells followed by a second verification operation to verify the second programming operation. A programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.