Nonvolatile Memory Dummy Cell Voltage Control
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Solution Overview
Problem
Existing nonvolatile memory devices face issues with erase failures due to sharp increases in horizontal electric fields between dummy cells and memory cells, leading to electron trapping by selection transistors.
Innovation Solution
The implementation of multiple dummy cells between selection transistors and memory cells, with different voltage levels applied to these dummy cells to reduce the horizontal electric field and prevent electron trapping, thereby minimizing erase failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dummy cells are added between selection transistors and memory cells, then electron trapping is prevented and erase reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the single dummy cell into multiple dummy cells (first dummy cell and second dummy cell) positioned at different locations between the selection transistor and memory cells. This segmentation allows each dummy cell to independently manage electric field control in different regions, preventing electron trapping more effectively while maintaining a modular structure that simplifies the overall design process.
Solution Approach 2:
Different voltage levels are applied to different dummy cells based on their specific positions and functions. The first dummy cell receives a first voltage level while the second dummy cell receives a second voltage level, allowing localized optimization of electric field control in different regions of the memory string, thereby improving erase reliability without uniformly increasing complexity across the entire device.
2Reliability
If different voltage levels are applied to multiple dummy cells, then horizontal electric field is reduced and electron trapping is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary voltage levels to the dummy cells before the actual erase operation begins. By pre-establishing the appropriate voltage distribution across the multiple dummy cells, the horizontal electric field is controlled in advance, preventing electron trapping before it can occur during the erase operation, thereby reducing the precision demands during the critical erase phase.
Solution Approach 2:
The patent utilizes different voltage levels (first voltage level and second voltage level) applied to different dummy cells to dynamically control the electric field parameters. By changing the voltage parameters in a controlled manner across multiple dummy cells, the horizontal electric field is reduced effectively while distributing the precision requirements across multiple simpler voltage control points rather than requiring extreme precision at a single point.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces erase failures by controlling the electric field and preventing electron trapping, ensuring reliable data erasure in nonvolatile memory devices.
Implementation Method 1
different levels of voltages are provided to gates of the string dummy cells or to gates of the ground dummy cells to reduce a horizontal electric field generated between the string or ground selection transistor and the memory cells
Data Source
AI summary
A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells.