Semiconductor Memory Dummy Structures for Stress Management
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration levels and capacity while managing internal stress during manufacturing, particularly in the dummy regions where sufficient support for conductive and insulating layers is needed to prevent deformation.
Innovation Solution
The introduction of a semiconductor memory device design with larger area dummy structures in the dummy region compared to the contact region, and potentially using insulating layers and different dummy structure configurations, such as comb-shaped or larger width dummy structures, to effectively cancel out internal stresses and maintain structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration level and capacity of semiconductor memory devices are increased, then the storage capability is improved, but internal stress during manufacturing increases causing deformation
Solution Approach 1:
The patent applies local quality by creating dummy structures with different areas in different regions: larger area dummy structures in dummy regions and smaller area dummy structures in contact regions. This localized differentiation allows each region to have the appropriate level of stress compensation needed, preventing deformation in dummy regions while maintaining proper electrical connections in contact regions.
Solution Approach 2:
The patent implements preliminary anti-action by introducing dummy structures that generate internal stresses opposite to those generated by the memory cell structures. These dummy structures are positioned and sized to pre-compensate for the stress that would otherwise cause deformation during manufacturing, effectively counteracting the harmful stress before it can cause damage.
2Strength
If dummy structures with sufficient area are provided in dummy regions, then structural support is improved, but device complexity increases
Solution Approach 1:
The patent uses local quality by providing larger area dummy structures only in dummy regions where structural support is needed, while using smaller area dummy structures in contact regions where electrical connections are required. This selective approach provides necessary structural support without uniformly increasing complexity across the entire device.
Solution Approach 2:
The dummy structures serve multiple functions: they provide structural support to prevent deformation, generate compensating internal stresses, and maintain process compatibility. By making these structures multi-functional, the patent reduces the need for separate dedicated support structures, thereby limiting the increase in device complexity.
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.