Memory System Wear Leveling via Dummy Data Intermediary
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory devices face issues with wear leveling and read disturb due to uneven data distribution and frequent erasing, writing, and reading, which lead to reduced durability and data integrity.
Innovation Solution
A memory system comprising a cache memory, two nonvolatile semiconductor memory areas for page-level operations and block-level erasing, along with a management table and controller for allocating storage and managing data distribution to reduce wear and minimize read disturb by using dummy data for unwritten areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wear leveling is performed to equally distribute data update sections, then the durability of NAND flash memory is improved, but the complexity of data management increases
Solution Approach 1:
The patent introduces a dummy data mechanism as an intermediary between the host and the NAND flash memory. When a read request is received, the controller checks if the requested data is valid or dummy data, and only performs actual memory access if it's valid data. This intermediary layer simplifies the wear leveling process by allowing uniform treatment of all address spaces while maintaining durability benefits.
Solution Approach 2:
The patent changes the state parameter of memory cells by introducing a dummy data flag that distinguishes between valid and dummy data. This parameter change allows the system to perform wear leveling operations without actually reading or writing dummy data, thereby reducing unnecessary access cycles and simplifying data management complexity.
2Productivity
If readout operations are performed frequently, then data accessibility is improved, but read disturb phenomenon increases causing data instability
Solution Approach 1:
The patent applies preliminary action by pre-marking certain address ranges as dummy data areas before actual data is written there. When read requests target these pre-marked areas, the controller identifies them as dummy data and avoids actual memory access, thereby preventing read disturb before it can occur while still maintaining the appearance of data accessibility.
3Productivity
If erasing and writing operations are repeated many times, then data update capability is improved, but gate oxide film deterioration increases causing electron loss
Solution Approach 1:
The patent extracts the harmful aspect of repeated erasing and writing operations by identifying and isolating dummy data areas from actual data storage areas. By taking out dummy data access from the physical memory operations, the system can perform logical data updates without subjecting the gate oxide film to unnecessary stress, thereby preserving electron retention while maintaining data update capability.
4Speed
If unnecessary readout operations are performed on unwritten areas, then data retrieval speed is improved, but memory wear increases reducing device life
Solution Approach 1:
The patent implements feedback by continuously monitoring the validity status of data in each address range and using this information to control readout operations. When a read request is received, the system provides feedback by checking the validity flag and dynamically deciding whether to perform actual memory access or return dummy data, thereby preventing unnecessary wear while maintaining fast data retrieval for valid data.
Data Source
AI summary
A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.