Memory Read Circuit Using Dummy Word-Line Voltage Control
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Solution Overview
Problem
The challenge in DRAM design is to increase the sense margin during read operations without increasing the area of the peripheral circuit, as coupling capacitance between adjacent bit lines can reduce the accuracy of data read due to reduced sense margin.
Innovation Solution
The solution involves applying a first voltage to a selected word line to turn on the cell transistor of a memory cell and a second voltage to at least one dummy word line to turn on the cell transistor of a dummy memory cell, thereby adjusting the bit line capacitance to enhance the sense margin without increasing the peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sense margin is increased by adding more peripheral circuit components, then data read accuracy is improved, but the peripheral circuit area increases
Solution Approach 1:
The patent changes the voltage parameter applied to word lines. By applying a second voltage to dummy word lines in addition to the first voltage on the selected word line, the patent adjusts the bit line capacitance to increase the sense margin without adding physical circuit components, thereby improving data read accuracy while maintaining the same peripheral circuit area.
Solution Approach 2:
The patent introduces dummy word lines as intermediary elements that do not directly access memory cells but serve as mediators to adjust the bit line capacitance. These dummy word lines apply a second voltage to modify the electrical characteristics of the bit line, thereby enhancing the sense margin without requiring additional peripheral circuitry.
2Measurement precision
If the bit line capacitance is increased to improve sense margin, then data read accuracy is improved, but the peripheral circuit area increases
Solution Approach 1:
The patent modifies the electrical parameter of bit line capacitance by applying a second voltage to dummy word lines. This voltage adjustment changes the capacitance value dynamically without physically increasing the bit line structure or adding capacitor components, thereby improving the sense margin while keeping the peripheral circuit area constant.
Solution Approach 2:
The patent makes the bit line capacitance dynamic rather than fixed. By controlling the second voltage on dummy word lines, the capacitance can be adjusted during different operating conditions to optimize the sense margin, providing a flexible solution that does not require additional physical components.
Data Source
AI summary
Examples of the present disclosure disclose a memory and an operation method thereof, and a memory system. The memory includes: a memory cell array including a plurality of memory cells; bit lines coupled to the plurality of memory cells; a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit coupled to the bit lines and the word lines. The peripheral circuit is configured to apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line, and apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.