Memory Chip Duty Correction Circuits for Faster Clock Training
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Solution Overview
Problem
Existing memory devices face challenges in reducing duty correction circuit (DCC) training time and duty cycle degradation due to memory chip variations and channel variations, leading to performance degradation.
Innovation Solution
A memory device and controller configuration that includes multiple memory chips with duty correction circuits and sensing circuits, allowing for parallel duty correction operations during a dedicated training period, which corrects duty cycles and maintains performance even with increasing numbers of memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are used to increase storage capacity, then the storage capacity is improved, but the DCC training time increases and performance degradation occurs due to duty cycle variations
Solution Approach 1:
The system segments the duty correction process by providing separate duty correction circuits and sensing circuits for each memory chip. Each chip performs duty correction independently during the training period, allowing parallel processing that reduces total training time while maintaining storage capacity scaling
Solution Approach 2:
Duty correction operations are performed during a dedicated training period before normal operation begins. This preliminary action ensures that duty cycle variations are corrected in advance, preventing performance degradation during actual data transfer operations
2Quantity of substance
If more memory chips are added to the system, then the storage capacity is improved, but duty cycle degradation increases due to channel variation
Solution Approach 1:
Each memory chip includes a duty sensing circuit that monitors the duty cycle of its clock signal and provides feedback to a duty correction circuit. This feedback mechanism dynamically adjusts the clock signal to maintain a target duty cycle, compensating for channel variations that worsen with additional chips
Solution Approach 2:
Each memory chip has its own dedicated duty correction circuit and sensing circuit, allowing localized duty cycle correction tailored to each chip's specific channel characteristics. This local quality approach ensures that duty cycle stability is maintained independently for each chip regardless of the total number of chips in the system
3Measurement precision
If duty correction operations are performed sequentially for each memory chip, then the duty cycle accuracy is improved, but the total training time increases
Solution Approach 1:
The system segments the duty correction functionality into independent circuits for each memory chip, enabling parallel execution of duty correction operations during the training period while maintaining accurate duty cycle correction for each chip
Solution Approach 2:
Duty correction operations are concentrated into a periodic training period at the beginning of system operation. During this dedicated period, all duty correction activities occur in parallel, achieving both accuracy and speed without interfering with normal operational performance
Data Source
AI summary
A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.