Nonvolatile Memory Duty Correction via ZQ Calibration
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Solution Overview
Problem
High-speed data transfer in flash memory systems is hindered by signal distortion issues such as jitter, skew, and duty errors, particularly due to challenges in maintaining a desired duty ratio for the read enable signal, which complicates high-speed operations and increases power consumption.
Innovation Solution
A nonvolatile memory device and memory system that performs a duty correction operation using a ZQ calibration process to match impedance between the memory device and the memory controller, allowing for the generation of a clock with a corrected duty ratio, enabling reliable high-speed data transmission while minimizing power usage by only performing duty correction during high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty ratio correction is performed continuously to maintain signal integrity, then reliability is improved, but power consumption increases
Solution Approach 1:
The duty ratio correction operation is performed periodically only during high-speed read operations rather than continuously. The system detects whether a read operation is occurring and activates duty correction only when necessary, thereby maintaining signal integrity during critical operations while reducing power consumption during normal operations.
Solution Approach 2:
The system dynamically adjusts its behavior based on operational conditions. It monitors the read operation status and enables or disables duty ratio correction accordingly, allowing the system to adapt between high-reliability mode during high-speed reads and low-power mode during normal operations.
2Reliability
If duty ratio correction is performed during high-speed operations, then signal distortion is reduced, but device complexity increases
Solution Approach 1:
The duty ratio correction functionality is merged with the existing clock generation block and read operation circuitry. The correction mechanism shares resources with the clock generation block, and the overall system leverages the existing read operation infrastructure, thereby reducing the additional complexity burden.
Solution Approach 2:
The system uses feedback from the read operation status to control the duty ratio correction mechanism. The memory controller monitors whether a read operation is occurring and provides feedback to enable or disable the correction function, creating a closed-loop control that simplifies the overall system architecture.
Data Source
AI summary
A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation and a read operation in response to a ZQ calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.