Memory Duty-Cycle Detection Circuit With Comparator Offset Correction
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Solution Overview
Problem
NAND-type flash memory semiconductor devices face challenges in accurately correcting duty cycles of signals, leading to operational reliability issues due to variations in comparator threshold values and input offset voltages, which affect signal processing and data transmission.
Innovation Solution
The implementation of a detection circuit with a switching circuit and comparator that adjusts the duty cycle of signals by comparing voltage levels at different nodes, using a correction circuit to calculate and apply correction codes that account for input offset voltages, ensuring the duty cycle is maintained at approximately 50%, thereby reducing the influence of comparator offsets and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a comparator is used to detect duty cycle of signals, then duty cycle detection can be performed, but input offset voltages and threshold value variations cause measurement errors
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detection result is fed back to adjust the detection threshold dynamically. The detection circuit monitors the actual duty cycle of the signal and compares it with a reference value, then adjusts the comparator threshold to compensate for input offset voltages and manufacturing variations, thereby improving both measurement precision and operational reliability
Solution Approach 2:
The patent changes the operating parameters of the comparator by dynamically adjusting the detection threshold voltage based on the detected duty cycle. This parameter adjustment compensates for fixed offset voltages and threshold variations, allowing the system to maintain accurate duty cycle detection despite component variations
2Measurement precision
If duty cycle correction is implemented to maintain 50% duty cycle, then signal processing accuracy improves, but additional correction circuits and complexity are introduced
Solution Approach 1:
The patent merges the duty cycle detection function and correction control into a single integrated circuit block. The detection circuit simultaneously performs measurement and generates correction signals, eliminating the need for separate correction circuits and reducing overall device complexity while maintaining signal processing accuracy
Solution Approach 2:
The duty cycle correction system is designed to be self-regulating, where the detection circuit automatically adjusts the signal duty cycle without external intervention. The circuit uses its own output as feedback to maintain the 50% duty cycle target, reducing the need for additional control logic and simplifying the overall system
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.