Memory Device Duty Cycle Correction Circuit
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Solution Overview
Problem
Recent memory devices require significant time for both read duty cycle correct (RDCC) and write duty cycle correct (WDCC) training operations, as they perform these corrections based on different signals, leading to inefficiencies in data strobe signal processing.
Innovation Solution
A memory device is configured to perform WDCC using a signal generated based on the RDCC signal, allowing simultaneous execution of read and write duty cycle corrections by generating data strobe signals and dividing them to correct duty cycles for clock signals with different phases, thereby reducing the time and power required for duty cycle correct training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read duty cycle correct training and write duty cycle correct training are performed based on different signals, then correction accuracy for both read and write operations is improved, but training time increases significantly
Solution Approach 1:
The patent merges the read duty cycle correct training and write duty cycle correct training by having the write duty correction circuit use the data strobe signal generated during read duty correction training. This allows both training operations to be performed simultaneously on the same signal, reducing total training time while maintaining correction accuracy through dedicated correction circuits for each operation type.
Solution Approach 2:
The data strobe signal generated during read duty correction training is made multi-functional by using it as the basis for both read operation correction and write operation correction. The write duty correction circuit processes this same signal to correct write operation duty cycles, allowing one signal to serve multiple correction purposes simultaneously.
2Reliability
If separate training operations are performed for read and write duty cycle correction, then each operation receives dedicated correction attention, but power consumption increases
Solution Approach 1:
The patent combines the training operations by having the write duty correction circuit utilize the data strobe signal already generated during read duty correction training. This merging approach reduces power consumption by avoiding redundant signal generation and processing while maintaining dedicated correction capability through separate correction circuits that operate on the same signal foundation.
Data Source
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AI summary
Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.