Semiconductor Memory Duty Cycle Correction Circuit
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Solution Overview
Problem
Semiconductor memory devices, such as NAND flash memory, face challenges in maintaining optimal duty cycle correction for toggle signals, leading to inefficiencies in data transfer between the memory device and the memory controller, which can result in suboptimal data strobe signal duty cycles.
Innovation Solution
Incorporating a receiving circuit and correction circuit within the semiconductor memory device to adjust the duty cycles of read enable signals, using current sources to modify the signal timing and ensure a target duty cycle of 50% for the data strobe signals, thereby correcting the duty cycle of the toggle signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If duty cycle correction is performed externally, then device complexity is reduced, but data transfer efficiency deteriorates due to suboptimal toggle signal duty cycles
Solution Approach 1:
A duty cycle correction circuit is introduced as an intermediary component between the external signal source and the semiconductor memory device. This correction circuit adjusts the duty cycle of input signals before they reach the memory device, ensuring optimal toggle signal duty cycles for efficient data transfer while isolating the main memory device from complex duty cycle adjustment functionality.
Solution Approach 2:
The semiconductor memory device incorporates self-correction functionality through an internal duty cycle correction mechanism that automatically adjusts the duty cycle of received signals. This self-service approach allows the device to maintain optimal performance without requiring external intervention or complex external correction circuits, thereby improving data transfer efficiency while managing complexity internally.
2Productivity
If duty cycle correction circuit is added, then data transfer efficiency is improved, but device size increases
Solution Approach 1:
The duty cycle correction functionality is implemented in a localized manner within specific signal path segments rather than throughout the entire device. By concentrating correction functionality only where needed in the signal reception and processing path, the patent achieves improved data transfer efficiency while minimizing the additional device size required for correction circuitry.
3Loss of energy
If duty cycle correction is implemented, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The duty cycle correction mechanism operates by adjusting temporal parameters of signals (duty cycle, timing) rather than requiring complex circuit reconfiguration. This parameter-based approach allows for reduced power consumption through optimized signal characteristics while maintaining relatively simple manufacturing processes that deal with standard timing adjustments rather than complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that the duty cycle of the data strobe signals is maintained close to the target value, enhancing data transfer efficiency and reducing power consumption and device size.
Implementation Method 1
a correction circuit (60) that corrects duty cycles of the second toggle signal
Implementation Method 2
transistors (TR1 to TR9) and a capacitor (C10)
Data Source
AI summary
A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.