Memory Clock Duty Cycle Correction for Exact 180° Phase Shift
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining a 50% duty cycle ratio of the system clock, leading to irregular data output due to phase differences between the clock and its inverted clock, especially at high frequencies, which affects processing margins and stability.
Innovation Solution
A duty cycle correction circuit that generates corrected clocks with a substantially exact 180° phase difference between the clock and its inverted clock, using a clock edge detector and duty cycle ratio correcting unit to adjust the duty cycle ratios and ensure accurate phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the duty cycle ratio of the system clock is not 50%, then the processing margin for data output at rising and falling edges becomes different, but the data output stability deteriorates
Solution Approach 1:
The patent employs a duty cycle correction circuit that uses feedback mechanisms to continuously monitor and adjust the duty cycle ratio of the system clock. The circuit compares the actual duty cycle with the target 50% ratio and dynamically adjusts the clock signal to eliminate deviations, ensuring stable data output at both rising and falling edges.
Solution Approach 2:
The invention changes the duty cycle ratio parameter of the system clock from its original non-50% value to exactly 50% through the duty cycle correction circuit. This parameter transformation ensures equal processing margins for both rising and falling edge data operations, resolving the stability issue.
2Productivity
If the frequency of the system clock is increased to match the data processor speed, then the data input/output speed improves, but the phase difference between clock and inverted clock causes irregular data output
Solution Approach 1:
The patent introduces a duty cycle correction circuit as an intermediary component between the system clock source and the data output units. This intermediary circuit corrects the duty cycle ratio before the clock signal reaches the data output stages, ensuring that even at high frequencies, the clock maintains proper timing characteristics for regular data output.
3Reliability
If a duty cycle correction circuit is added to correct the duty cycle ratio to 50%, then the data output stability improves, but the device complexity increases
Solution Approach 1:
The patent merges the duty cycle correction functionality with existing clock distribution infrastructure in the memory device. By integrating the correction circuit into the existing clock management architecture rather than adding completely separate components, the design achieves duty cycle correction while minimizing the increase in overall device complexity.
Data Source
AI summary
A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.