Memory Clock Duty Adjustment With Separate Read and Write Training
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Solution Overview
Problem
High-speed DRAMs like LPDDR5 face challenges in correcting duty cycle distortions, which affect data output validity and margin characteristics, particularly in separating write and read paths, leading to difficulties in optimizing read clock duty and improving read margin characteristics.
Innovation Solution
A memory device with registers for storing code values and a duty cycle monitor that performs separate training on write and read paths to adjust the data transmission clock, allowing for independent duty cycle adjustments and compensation, thereby distinguishing clock duty information for write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate training is performed on write and read paths, then read margin characteristics are improved, but device complexity increases due to additional training mechanisms
Solution Approach 1:
The patent divides the training process into separate write path training and read path training operations. The duty cycle monitor independently monitors write clock duty cycle during write path training and read clock duty cycle during read path training, allowing each path to be optimized separately for improved read margin characteristics while maintaining manageable complexity through modular training sequences
Solution Approach 2:
The patent performs preliminary duty cycle monitoring and code value determination during training modes before actual data operations. The duty cycle adjuster pre-adjusts the clock duty cycle based on training results, storing optimal code values in registers that are then applied during normal read/write operations, eliminating the need for complex real-time adjustments
2Reliability
If duty cycle adjustment is optimized for read path, then data output validity is improved, but the system loses versatility in simultaneously optimizing both read and write paths
Solution Approach 1:
The patent implements dynamic duty cycle adjustment where the duty cycle adjuster can independently select between different code values stored in registers based on operation mode. During read operations, the system uses code values optimized for read path duty cycle, while during write operations, it uses code values optimized for write path, providing adaptive optimization for both paths without compromising either
Solution Approach 2:
The patent changes the duty cycle parameter independently for read and write paths by loading different code values from separate registers into the duty cycle adjuster. The system maintains multiple code values representing different duty cycle adjustments, selecting the appropriate set based on whether the current operation is read or write, thereby optimizing data output validity for reads while preserving write path performance
Data Source
AI summary
A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.