Semiconductor Memory Medium Dynamic Verify Voltage Control
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Solution Overview
Problem
Current semiconductor memory systems face limitations in efficiently managing multiple write operations on a single memory cell within a given period without requiring an erase operation, leading to reduced data storage capacity and increased wear on memory chips.
Innovation Solution
The system executes multiple program and verify operations on a memory cell within a specific period, adjusting the verify voltage based on the number of write operations, allowing for multiple SLC write operations without immediate erasure, and utilizing a 'Number of written times after erasure' table to manage memory cell states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple write operations are performed on a memory cell within a period from erasure to next erasure, then data storage capacity is improved, but memory chip wear increases
Solution Approach 1:
The patent applies dynamics by making the verify voltage adjustable based on the number of write operations performed. The verify voltage is dynamically changed according to the write operation count, allowing the system to adapt to different wear states and optimize between storage capacity and reliability
Solution Approach 2:
The patent changes the verify voltage parameter based on the number of write operations. By adjusting this electrical parameter dynamically, the system can accommodate multiple write operations while managing the wear on memory cells, thus resolving the contradiction between storage capacity and chip reliability
2Productivity
If verify voltage is adjusted based on number of write operations, then multiple write operations without erasure are enabled, but device complexity increases
Solution Approach 1:
The patent implements self-service by using the memory cell array itself to store the number of write operations information. This eliminates the need for external counters or additional control circuits, as the memory cells automatically track and record the write operation count, thereby reducing overall device complexity while maintaining high productivity
Data Source
AI summary
According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.