Memory ECC Address Auto-Generation for Deterministic Latency
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Solution Overview
Problem
Conventional memory management systems face bandwidth and latency issues due to communication between memory controllers and devices, which can lead to unreliable performance in applications requiring accuracy and speed, such as autonomous driving and medical equipment, where multiple commands for data and error correction code (ECC) retrieval cause non-deterministic timing and potential failures.
Innovation Solution
A memory device with a memory interface and ECC generation component that automatically establishes an address for ECC information based on data access requests, allowing for deterministic latency by transferring data and ECC information in a single burst, with optional external address generation and selective engagement of ECC components, optimizing storage capacity utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple commands are issued for memory access to retrieve data and ECC information, then data accuracy is improved through ECC, but access latency increases and timing becomes non-deterministic
Solution Approach 1:
The patent combines data access and ECC information access into a single memory operation. The memory device automatically generates an ECC address based on the data address, allowing both data and ECC to be retrieved in one burst operation rather than requiring separate commands for each, thereby reducing latency while maintaining accuracy
Solution Approach 2:
The memory device pre-calculates and reserves storage locations for ECC information based on the data address before the actual access operation. This preliminary address generation and reservation allows the ECC information to be ready immediately when the data is accessed, eliminating additional processing time and ensuring deterministic timing
2Speed
If communication bus size is increased to resolve bandwidth issues, then data transfer speed is improved, but system cost and resource consumption increase
Solution Approach 1:
Instead of increasing the communication bus width (horizontal dimension), the patent utilizes the memory address space (vertical dimension) to store ECC information at predetermined locations. This allows ECC data to be accessed through the existing address bus without requiring additional communication bandwidth, effectively solving the bandwidth issue without increasing system cost
3Reliability
If ECC information is stored in reserved memory regions, then data integrity is improved, but storage capacity is reduced
Solution Approach 1:
The patent implements local quality by creating dedicated reserved regions within the memory array specifically for ECC information storage. These reserved regions are strategically positioned to be automatically accessible during data operations, ensuring data integrity without requiring a separate memory subsystem that would significantly impact overall storage capacity
Data Source
AI summary
The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a memory device comprises a memory interface, an ECC generation component, and storage components. The memory interface is configured to receive an access request to an address at which data is stored. The memory interface can also forward responses to the request including the data and ECC information associated with the data. The ECC generation component is configured to automatically establish an address at which the ECC information is stored based upon the receipt of the access request to an address at which data is stored. In one exemplary implementation, the internal establishment of the address at which the ECC information is stored is automatic. The storage components are configured to store the information.