Memory Write-Read Circuit Using Address-Based ECC Modification
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Solution Overview
Problem
Existing data storage techniques face challenges in accurately writing and reading data from memory while ensuring error detection and correction, particularly due to the need for additional error handling code and the risk of errors occurring during write and read operations.
Innovation Solution
A writing circuit and method that generate modified extended write data by combining write data and error handling code, reversible based on address information, and a reading circuit that reversibly modifies read data to detect errors using the same error handling code, allowing for error detection and correction without additional memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error handling code is concatenated to data word for error detection and correction, then error detection capability is improved, but memory space requirement increases
Solution Approach 1:
The patent combines the error handling code with the address information by XORing them together to form a single modified address value. This merging eliminates the need for separate storage of error handling code, as it is now embedded within the address structure itself. The modified address serves dual purposes: addressing the memory location and containing the error detection capability.
Solution Approach 2:
The address information is given multiple functions: it serves as the memory location identifier and simultaneously carries the error handling code. By making the address multi-functional, the patent eliminates the need for additional dedicated storage space for error handling code, as the same address structure performs both addressing and error detection roles.
2Reliability
If error handling code is stored separately from data word, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error handling code with the address information into a single integrated structure. Instead of maintaining separate storage and processing paths for data and error code, the invention combines them into the address value itself, simplifying the overall device architecture by reducing the number of separate components and operations needed.
3Reliability
If address information is used to reversibly modify extended write data, then error detection capability is improved, but manufacturing precision requirement increases
Solution Approach 1:
The patent changes the parameter of the address information by applying a reversible modification operation (XOR) that transforms the original address into a modified address containing embedded error handling code. This parameter transformation allows the system to encode error detection capability within the existing address structure without requiring additional precision in manufacturing or encoding processes.
Data Source
AI summary
A writing circuit for writing write data into a memory comprises an evaluator configured for providing an error handling code on the basis of the write data. A modifier reversibly modifies extended write data comprising both the write data and the error handling code in dependence on address information related to a writing address in order to provide modified extended write data. A writer writes the modified extended write data in a position of the memory defined by a writing address. A reading circuit for reading extended read data from a memory comprises a reader configured for reading the extended read data from a position of the memory defined by a reading address. A de-modifier modifies the extended read data in dependence on address information related to a reading address in order to provide extracted read data and an extracted error handling code. An error-detector detects based on the extracted error handling code whether the extracted read data comprises an error.