Memory Error Detection Layer for ECC Aliasing Protection
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Solution Overview
Problem
Existing memory systems face challenges in reliably detecting and correcting errors, particularly when error correction procedures introduce aliasing errors or fail to detect higher-order errors such as triple-bit errors, leading to undetected or uncorrected errors in data transmission and storage.
Innovation Solution
Implementing a host device capable of performing error detection procedures that can reliably detect up to three errors in data, and corresponding error correction procedures to correct single-bit errors, while also generating and using parity information to detect and correct errors introduced during data storage and transmission, thereby preventing aliasing and ensuring data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction procedures are implemented to correct single-bit errors, then reliability is improved, but aliasing errors may be introduced that go undetected
Solution Approach 1:
The patent introduces an intermediary error detection code (EDC) that operates between the error correction code (ECC) and the data. The EDC checks for higher-order errors including aliasing errors before the ECC corrects single-bit errors, preventing the ECC from mistakenly correcting undetected higher-order errors. This intermediary detection layer resolves the contradiction by identifying harmful aliasing errors that would otherwise go undetected while maintaining the beneficial single-bit error correction capability.
2Reliability
If traditional error correction codes are used, then single-bit errors are corrected, but higher-order errors such as triple-bit errors cannot be detected
Solution Approach 1:
The patent segments the error handling function into two distinct components: an error detection code (EDC) for detecting higher-order errors and an error correction code (ECC) for correcting single-bit errors. The EDC specifically targets higher-order errors including triple-bit errors, while the ECC handles single-bit corrections. This segmentation resolves the contradiction by assigning different detection capabilities to different code components, enabling both single-bit correction and higher-order error detection without requiring a single complex code to do both.
3Device complexity
If no error detection procedure is performed, then device complexity is reduced, but undetected errors compromise data integrity
Solution Approach 1:
The patent implements partial error detection by focusing the EDC specifically on detecting higher-order errors and aliasing errors rather than attempting to detect and correct all possible error types. The EDC performs a targeted check for uncorrectable errors before the ECC attempts correction, providing sufficient detection capability for critical error types without implementing a full-featured error correction system. This partial action approach maintains reasonable device complexity while significantly improving data integrity for the most dangerous error types.
Data Source
AI summary
Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.