Memory Device ECC Circuit Parallel Bank Error Correction
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Solution Overview
Problem
As semiconductor memory devices shrink in process scale, their integration increases, leading to a rapid rise in bit error rates, which existing technologies struggle to address effectively through error correction codes (ECC).
Innovation Solution
A memory device with a memory cell array, control logic, and an ECC circuit that includes a syndrome generator, parity generator, and syndrome decoder to correct errors by generating and applying parity to data, allowing for error detection and correction across multiple memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process scale is reduced to increase integration degree, then integration degree is improved, but bit error rate increases
Solution Approach 1:
The memory device is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each capable of simultaneous operation. This segmentation allows parallel processing of read and write operations across different banks, improving overall system throughput while maintaining error correction capabilities for each individual bank
Solution Approach 2:
The ECC circuit performs preliminary error detection and correction operations on read data before it is fully processed. The syndrome generator and syndrome decoder are configured to detect and correct errors in advance during the data readout process, preventing error propagation to subsequent operations
2Reliability
If ECC operations are performed sequentially across memory banks, then error correction accuracy is improved, but operation speed decreases
Solution Approach 1:
The memory system is segmented into multiple independently operable banks, each with its own ECC protection. This allows the ECC operations to be performed in parallel across different banks rather than sequentially, maintaining error correction accuracy while significantly improving throughput by utilizing multiple banks simultaneously
Solution Approach 2:
While ECC operations are being performed on data from one memory bank, the system continuously performs other useful actions such as reading data from or writing data to other memory banks. This continuous operation ensures that the ECC processing for one bank does not create idle time in the overall system, maintaining high utilization and speed
3Productivity
If multiple memory banks operate simultaneously, then productivity is improved, but device complexity increases
Solution Approach 1:
The control logic is designed as a universal controller that can manage multiple memory banks using the same control signals and protocols. Each memory bank follows the same operational pattern for read, write, and ECC operations, allowing the control logic to handle multiple banks without requiring bank-specific control circuits, thus managing complexity while enabling parallel operation
Data Source
AI summary
A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.