Semiconductor Memory ECC Engine for Bit Error Correction
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Solution Overview
Problem
As DRAMs decrease in size, bit errors in memory cells increase rapidly, leading to decreased yield and operational issues in volatile memory devices, which existing technologies have not effectively addressed.
Innovation Solution
Incorporating an error correction code (ECC) engine within semiconductor memory devices to detect and correct error bits in read data, with a channel interface circuit transmitting a decoding status flag to the memory controller, allowing for real-time error management and improved data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM size is decreased to increase storage density, then storage capacity is improved, but bit error rate increases rapidly
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction before data is fully processed or lost. The ECC engine detects and corrects bit errors in read data before the data is used by the memory controller, preventing error propagation and ensuring data integrity despite increased bit error rates from smaller memory cell sizes.
Solution Approach 2:
The patent introduces an intermediary component - the ECC (Error Correction Code) engine - that sits between the memory cell array and the memory controller. This intermediary detects and corrects bit errors in read data, acting as a mediator that protects the system from the increased error rates inherent in scaled-down memory cells while maintaining high storage density.
2Quantity of substance
If DRAM size is decreased to increase storage density, then storage capacity is improved, but manufacturing yield decreases
Solution Approach 1:
The patent applies self-service by enabling the memory device to automatically detect and correct its own errors through the integrated ECC engine. The memory device performs self-diagnosis and self-correction of bit errors, eliminating the need for external intervention or re-manufacturing of defective devices, thereby improving effective yield despite smaller cell sizes.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing error correction coding. This parameter change allows the memory device to operate reliably at smaller dimensions by compensating for increased variability and error rates through mathematical correction codes, effectively improving yield without requiring larger manufacturing tolerances.
3Reliability
If ECC engine is added to detect and correct errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the ECC engine directly into the memory device structure, combining error correction functionality with the existing memory architecture. The ECC engine is merged with the memory cell array and channel interface circuit, creating a unified system that provides error correction without requiring separate external components, thus managing complexity while maintaining reliability.
Solution Approach 2:
The patent applies universality by designing the ECC engine to handle multiple error scenarios and memory operations within a single integrated component. The channel interface circuit is configured to work with the ECC engine across different read operations, providing universal error protection throughout the memory device without requiring separate specialized circuits for each function.
Data Source
AI summary
A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.